Wafer-level vacuum package with vertical feed throughs

被引:11
|
作者
Chae, J [1 ]
Giachino, JM [1 ]
Najafi, K [1 ]
机构
[1] Univ Michigan, Ann Arbor, MI 48109 USA
关键词
packaging; Pirani gauge; vertical feedthroughs; vacuum package;
D O I
10.1109/MEMSYS.2005.1453988
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper reports a MEMS vacuum package with vertical feedthroughs formed in a glass substrate all at the wafer level. This approach satisfies requirements for MEMS vacuum packages, including small size, vacuum/hermetic capability, sealed and low parasitic feedthroughs, wafer level processing, compatibility with most MEMS processes, and low cost. It also enables flipchip solder attachment to a PC board. The package has an integrated micro-Pirani gauge on a glass substrate for in-situ monitoring, silicon cap, and vertical feedthroughs through the glass. The integrated Pirani gauge has 0.6mTorr resolution at 0.1Torr and 0.2Torr resolution at 100Torr. Using the Pirani gauge, we have achieved similar to 1 1Torr base pressure inside the vacuum package without a getter. Another package sealed at similar to 80Torr has maintained its pressure for more than 2 months.
引用
收藏
页码:548 / 551
页数:4
相关论文
共 50 条
  • [1] Fabrication and characterization of a wafer-level MEMS vacuum package with vertical feedthroughs
    Chae, Junseok
    Giachino, Joseph M.
    Najafi, Khalil
    [J]. JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, 2008, 17 (01) : 193 - 200
  • [2] Fabrication and Testing of a Wafer-Level Vacuum Package for MEMS Device
    Premachandran, C. S.
    Chong, Ser Choong
    Liw, Saxon
    Nagarajan, Ranganathan
    [J]. IEEE TRANSACTIONS ON ADVANCED PACKAGING, 2009, 32 (02): : 486 - 490
  • [3] Wafer-level package interconnect options
    Balachandran, Jayaprakash
    Brebels, Steven
    Carchon, Geert
    Kuijk, Maarten
    De Raedt, Walter
    Nauwelaers, Bart K. J. C.
    Beyne, Eric
    [J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2006, 14 (06) : 654 - 659
  • [4] Wafer-level vacuum package of two-dimensional micro-scanner
    Hoang Manh Chu
    Sasaki, Takashi
    Hane, Kazuhiro
    [J]. MICROSYSTEM TECHNOLOGIES-MICRO-AND NANOSYSTEMS-INFORMATION STORAGE AND PROCESSING SYSTEMS, 2018, 24 (05): : 2159 - 2168
  • [5] Wafer-level vacuum package of two-dimensional micro-scanner
    Hoang Manh Chu
    Takashi Sasaki
    Kazuhiro Hane
    [J]. Microsystem Technologies, 2018, 24 : 2159 - 2168
  • [6] Wafer-level vacuum packaging for MEMS
    Gooch, R
    Schimert, T
    McCardel, W
    Ritchey, B
    Gilmour, D
    Koziarz, W
    [J]. JOURNAL OF VACUUM SCIENCE & TECHNOLOGY A-VACUUM SURFACES AND FILMS, 1999, 17 (04): : 2295 - 2299
  • [7] Wafer-level hermetic package with through-wafer interconnects
    Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050, China
    不详
    [J]. J Fun Mater Dev, 2006, 6 (469-473):
  • [8] A Wafer-Level Vacuum-Packaged Vertical Resonant Electric Field Microsensor
    Gao, Yahao
    Liu, Xiangming
    Peng, Simin
    Zhang, Wei
    Liu, Yufei
    Wang, Yao
    Wu, Zhengwei
    Peng, Chunrong
    Xia, Shanhong
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2024, 71 (01) : 782 - 789
  • [9] Low-temperature vacuum hermetic wafer-level package for uncooled microbolometer FPAs
    Garcia-Blanco, S.
    Topart, P.
    Desroches, Y.
    Caron, J. S.
    Williamson, F.
    Alain, C.
    Jerominek, H.
    [J]. RELIABILITY, PACKAGING, TESTING, AND CHARACTERIZATION OF MEMS/MOEMS VII, 2008, 6884
  • [10] Heat Dissipation Capability of a Package-on-Package Embedded Wafer-Level Package
    Han, Yong
    Lau, Boon Long
    Jung, Boo Yang
    Zhang, Xiaowu
    [J]. IEEE DESIGN & TEST, 2015, 32 (04) : 32 - 39