Implementation of A High Speed Multiplier for High-Performance and Low Power Applications

被引：0

作者：

Kumar, G. Ganesh ^{[1
]}

Sahoo, Subhendu K. ^{[1
]}

机构：

[1] BITS Pilani, Dept Elect & Elect Engn, Hyderabad Campus, Pilani 500078, Rajasthan, India

来源：

2015 19TH INTERNATIONAL SYMPOSIUM ON VLSI DESIGN AND TEST (VDAT) | 2015年

关键词：

Vedic multiplier; carry save array; power-delay product; carry-select adder;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The performance of multiplication in terms of speed and power is crucial for most of the Digital Signal Processing (DSP) applications. Many researchers have come up with various multipliers such as array, Booth, carry save, Wallace tree and modified Booth multipliers. However, for the present day applications Vedic multipliers based on Vedic Mathematics are presently under focus due to their high speed and low power consumption. In this paper, we propose a design of 8 and 16-bit multipliers using fast adders (carry save adder, BrentKung adder and carry-select adder) to minimize the powerdelay product of multipliers intended for high-performance and low-power applications. Implementation results demonstrate that the proposed Vedic multipliers with fast adders really achieve significant improvement in delay, and power-delay product when compared with the conventional multipliers.

引用

页数：4

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