Software-based Gate-level Information Flow Security for IoT Systems

被引:8
|
作者
Cherupalli, Hari [1 ]
Duwe, Henry [2 ]
Ye, Weidong [3 ]
Kumar, Rakesh [3 ]
Sartori, John [1 ]
机构
[1] Univ Minnesota, Minneapolis, MN 55455 USA
[2] Iowa State Univ, Ames, IA USA
[3] Univ Illinois, Chicago, IL 60680 USA
关键词
ultra-low-power processors; security; information flow; hardware-software co-analysis; Internet of Things; TRACKING;
D O I
10.1145/3123939.3123955
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
The growing movement to connect literally everything to the internet (internet of things or IoT) through ultra-low-power embedded microprocessors poses a critical challenge for information security. Gate-level tracking of information flows has been proposed to guarantee information flow security in computer systems. However, such solutions rely on non-commodity, secure-by-design processors. In this work, we observe that the need for secure-by-design processors arises because previous works on gate-level information flow tracking assume no knowledge of the application running in a system. Since IoT systems typically run a single application over and over for the lifetime of the system, we see a unique opportunity to provide application-specific gate-level information flow security for IoT systems. We develop a gate-level symbolic analysis framework that uses knowledge of the application running in a system to efficiently identify all possible information flow security vulnerabilities for the system. We leverage this information to provide security guarantees on commodity processors. We also show that security vulnerabilities identified by our analysis framework can be eliminated through software modifications at 15% energy overhead, on average, obviating the need for secure-by-design hardware. Our framework also allows us to identify and eliminate only the vulnerabilities that an application is prone to, reducing the cost of information flow security by 3.3x compared to a software-based approach that assumes no application knowledge.
引用
收藏
页码:328 / 340
页数:13
相关论文
共 50 条
  • [1] Gate-Level Information Flow Tracking for Security Lattices
    Hu, Wei
    Mu, Dejun
    Oberg, Jason
    Mao, Baolei
    Tiwari, Mohit
    Sherwood, Timothy
    Kastner, Ryan
    [J]. ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2014, 20 (01) : 1 - 25
  • [2] Static Gate-Level Information Flow for Hardware Information Security with Bounded Model Checking
    Zhao, Yiqiang
    Qu, Gonsen
    Zhang, Qizhi
    Li, Yao
    Li, Zhengyang
    He, Jiaji
    [J]. 2024 IEEE 42ND VLSI TEST SYMPOSIUM, VTS 2024, 2024,
  • [3] GATE-LEVEL INFORMATION-FLOW TRACKING FOR SECURE ARCHITECTURES
    Tiwari, Mohit
    Li, Xun
    Wassel, Hassan M. G.
    Mazloom, Bita
    Mysore, Shashidhar
    Chong, Frederic T.
    Sherwood, Timothy
    [J]. IEEE MICRO, 2010, 30 (01) : 92 - 100
  • [4] Software-based Security Systems in Glass Production
    Isik, Deniz
    [J]. ATP MAGAZINE, 2019, (08): : 40 - 42
  • [5] A logic obfuscation attack method based on gate-level information flow tracing techniques
    Liu, Liang
    Zhu, Jiacheng
    Zhang, Zhe
    Shen, Lixiang
    Sun, Yufeng
    Mu, Dejun
    [J]. Xibei Gongye Daxue Xuebao/Journal of Northwestern Polytechnical University, 2024, 42 (01): : 78 - 83
  • [6] Detecting Hardware Trojans with Gate-Level Information-Flow Tracking
    Hu, Wei
    Mao, Baolei
    Oberg, Jason
    Kastner, Ryan
    [J]. COMPUTER, 2016, 49 (08) : 44 - 52
  • [7] Security Order of Gate-Level Masking Schemes
    Takarabt, Sofiane
    Bahrami, Javad
    Ebrahimabadi, Mohammad
    Guilley, Sylvain
    Karimi, Naghmeh
    [J]. 2023 IEEE INTERNATIONAL SYMPOSIUM ON HARDWARE ORIENTED SECURITY AND TRUST, HOST, 2023, : 57 - 67
  • [8] Arbitrary Precision and Complexity Tradeoffs for Gate-Level Information Flow Tracking
    Becker, Andrew
    Hu, Wei
    Tai, Yu
    Brisk, Philip
    Kastner, Ryan
    Ienne, Paolo
    [J]. PROCEEDINGS OF THE 2017 54TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2017,
  • [9] Exploiting behavioral information in gate-level ATPG
    Chiusano, S
    Corno, F
    Prinetto, P
    [J]. JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 1999, 14 (1-2): : 141 - 148
  • [10] Gate-Level Characterization: Foundations and Hardware Security Applications
    Wei, Sheng
    Meguerdichian, Saro
    Potkonjak, Miodrag
    [J]. PROCEEDINGS OF THE 47TH DESIGN AUTOMATION CONFERENCE, 2010, : 222 - 227