A 450 MS/s 10-bit Time-Interleaved Zero-Crossing Based ADC

被引：0

作者：

Chu, J. ^{[1
]}

Lee, H. -S. ^{[1
]}

机构：

[1] MIT, Cambridge, MA 02139 USA

来源：

2011 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC) | 2011年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 450-MS/s 10-bit time-interleaved zero-crossing based pipelined ADC is described. The prototype ADC, fabricated in a 90-nm CMOS process, occupies 1.3 mm(2). A reference pre-charging technique is applied to reduce the voltage ripples on the reference voltages. Gain, offset, and timing calibration is applied to achieve an 8.7 ENOB with a 211 MHz input signal and dissipates 34 mW from a 1.2V supply for a FOM of 182 fJ/step.

引用

页数：4

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