MUX based flash ADC for reduction in number of comparators

被引：0
|
作者：
Modi, Vivek [1 ]
Bhargava, Cherry [1 ]
Rathour, Navjot [1 ]
Bansal, Sandeep [1 ]
机构：
[1] Lovely Profess Univ, Sch Elect & Elect Engn, Phagwara, India
来源：
2ND INTERNATIONAL CONFERENCE ON INTELLIGENT CIRCUITS AND SYSTEMS (ICICS 2018) | 2018年
关键词：
Flash ADC; multiplexer; number of comparators; SFDR; ENOB; TO-DIGITAL CONVERTER; DESIGN;
D O I：
10.1109/ICICS.2018.00023
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A conventional N-bit flash analog to digital converter has been required the 2(N) number of resistors and 2(N)-1 number of preamplifiers as well as comparators. In this proposed work, a number of comparators could be reduced by introducing the multiplexer (MUX). This proposed work has only required the (2((N-2)) + 1) number of comparators. For 6-bit resolution, MUX based flash ADC requires a reduced number of comparators by 73%, respectively, compared with the traditional flash ADC. This proposed 6-bit ADC consists of a reference ladder circuit, a (2x1) multiplexer, 8 (4x1) multiplexer, 17 comparators and thermometer to binary encoder. The proposed 6-bit 200 MSPS ADC is designed and simulated in cadence tools with 1 V supply voltage using 90nm CMOS technology. The proposed work results into effective number of bits (ENOB) of 5.69 bit and figure of merit (FOM) of 0.019 pJ/conversion-step for 200 MS/s.
引用
收藏
页码：52 / 57
页数：6
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