Process induced bias: A study of resist design and process implications

被引:0
|
作者
Fonseca, Carlos [1 ]
Scheer, Steven [1 ]
Carcasi, Mike [1 ]
Shibata, Tsuyoshi [2 ]
Otsuka, Takahisa [2 ]
机构
[1] Tokyo Electron Amer Inc, 2400 Grove Blvd, Austin, TX 78741 USA
[2] Tokyo Electron Kyushu Ltd, Kumamoto 8611116, Japan
关键词
D O I
10.1117/12.773187
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
Critical dimension uniformity (CDU) has both across field and across wafer components. CD error generated by across wafer etching non-uniformity and other process variations can have a significant impact on CDU. To correct these across wafer variations, compensation by exposure dose(1) and/or PEB temperature(2,3) have been proposed. These compensation strategies often focus on a specific structure without evaluating how process compensation impacts the CDU of all structures to be printed in a given design. In a previous study(4), the authors evaluated the relative merits of across wafer dose and PEB temperature compensation on the process induced CD bias and CDU. For the process studied, both metrics demonstrated that using PEB temperature to control across wafer CD variation was preferable to using dose compensation. The previous study was limited to a single resist and variations to track and scanner processing were kept to a minimum. Further examination of additional resist materials has indicated that significant variation in dose and PEB temperature induced CD biases exist from material to material. It is the goal of this work to understand how resist design, as well as track and scanner processing, impact process induced bias (PIB). This is accomplished by analyzing full resist models for a range of resists that exhibit different dose and PEB temperature PIB behavior. From these models, the primary resist design contributors to PIB are isolated. A sensitivity analysis of the primary resist design as well as track and scanner processing effects will also be simulated and presented.
引用
收藏
页数:12
相关论文
共 50 条
  • [31] LWR Improvement in EUV Resist Process
    Koh, Chawon
    Kim, Hyun-Woo
    Kim, Sumin
    Na, Hai-Sub
    Park, Chang-Min
    Park, Cheolhong
    Cho, Kyoung-Yong
    EXTREME ULTRAVIOLET (EUV) LITHOGRAPHY II, 2011, 7969
  • [32] Simulation benchmarldng for the whole resist process
    Kim, SK
    Lee, JE
    Park, SW
    Yoo, JY
    Oh, HK
    DATA ANALYSIS AND MODELING FOR PROCESS CONTROL, 2004, 5378 : 58 - 64
  • [33] Study of the design process model
    Zhao, Ke
    Li, Weidong
    Ye, Shanghui
    Xi'an Dianzi Keji Daxue Xuebao/Journal of Xidian University, 25 (01): : 85 - 89
  • [34] STUDY OF CONTROLLABILITY IN PROCESS DESIGN
    FONYO, Z
    GROSS, F
    CHEMIE INGENIEUR TECHNIK, 1992, 64 (08) : 738 - 739
  • [35] Implications of Alternative Multilevel Design Methods for Design Process Management
    Shahan, David
    Seepersad, Carolyn C.
    CONCURRENT ENGINEERING-RESEARCH AND APPLICATIONS, 2010, 18 (01): : 5 - 18
  • [36] Bias in the review process
    Primack, Richard B.
    Marrs, Rob
    BIOLOGICAL CONSERVATION, 2008, 141 (12) : 2919 - 2920
  • [37] Plasma induced substrate damage in high dose implant resist strip process
    Chan, BW
    Perng, BC
    Sheu, L
    Chiu, YH
    Tao, HJ
    2003 8TH INTERNATIONAL SYMPOSIUM ON PLASMA- AND PROCESS-INDUCED DAMAGE, 2003, : 73 - 76
  • [38] Spin on Lithographic Resist Trim Process Optimization and Process Window Evaluation
    Karanikas, Christos F.
    Taylor, J. Christopher
    Vaduri, Naveen
    Islam, Tafsirul
    ADVANCES IN PATTERNING MATERIALS AND PROCESSES XXXI, 2014, 9051
  • [39] STUDY ON ASHING PROCESS FOR REMOVAL OF ION-IMPLANTED RESIST LAYER
    FUJIMURA, S
    KONNO, J
    YANNO, H
    TAKADA, T
    INAYOSHI, K
    JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 1987, 134 (8B) : C454 - C454
  • [40] Process window overlap for posts and lines and spaces: Optimization by resist type, optical settings and mask bias
    Reilly, MT
    Kvam, K
    Willie, J
    LITHOGRAPHY FOR SEMICONDUCTOR MANUFACTURING, 1999, 3741 : 40 - 45