A 2-nW 1.1-V self-biased current reference in CMOS technology

被引：131

作者：

Camacho-Galeano, EM ^{[1
]}

Galup-Montoro, C ^{[1
]}

Schneider, MC ^{[1
]}

机构：

[1] Univ Fed Santa Catarina, Dept Elect Engn, BR-88040900 Florianopolis, SC, Brazil

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2005年 / 52卷 / 02期

关键词：

CMOS analog integrated circuit; current source; low voltage; proportional to absolute temperature (PTAT) voltage;

D O I：

10.1109/TCSII.2004.842059

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents the design of an ultra-low-power self-biased 400-pA current source. We propose the use of a very simple topology along with a design methodology based on the concept of inversion level. An efficient design methodology has resulted in a cell area around 0.045 mm(2) in the AMI 1.5-mum CMOS technology and power consumption around 2 nW for 1.2-V supply. Simulated and experimental results validate the design and show that the current source can operate at supply voltages down to 1.1 V with a good regulation (< 6%/V variation of the supply voltage) in a 1.5-mum technology.

引用

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页码：61 / 65

页数：5

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