Design of Asynchronous High Throughput SHA-256 Hardware Accelerator in 40nm CMOS

One of the major issues in implementation of hash functions algorithm is how to decrease the critical path delay and required area effectively. How to expand flexibility, generality and integrity are also important issues as well. As more information are stored and processed on the general-purpose microcontroller in the edge of internet of things (IoT), more efficient data encryption must be ensured. Before encryption of large data sets, it is preferred that the encryption is adapt to asynchronous operation for different volume and arrival data rate. In this paper, an asynchronous SHA-256 hardware accelerator with 32 computation clock cycles for each block is proposed and is at liberty to buffer intermediate hash values, which provides high throughput, robust transmission, adjustable computation frequency and is also easily integrated to microcontroller. The proposed design was implemented in SMIC 40nm technology and performed simulation and verification with Synopsys VCS. The results of post-synthesis simulation show the throughput up to 3.6Gbps.