Design and implementation of FPGA configuration logic block using asynchronous semi-static NCL circuits

被引：0

作者：

Dugganapally, Indira P. ^{[1
]}

Al-Assadi, Waleed K. ^{[1
]}

Pillai, Vijay ^{[2
]}

Smith, Scott ^{[2
]}

机构：

[1] Missouri Univ Sci & Technol, Dept Elect & Comp Engn, 301 W 16th St, Rolla, MO 65409 USA

[2] Univ Arkansas, Dept Elect Engn, Fayetteville, AR 72701 USA

来源：

2008 IEEE REGION 5 CONFERENCE | 2008年

基金：

美国国家科学基金会;

关键词：

Configurable Logic Block (CLB); field programmable gate array (FPGA); NULL Convention Logic (NCL); look up table (LUT);

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper proposes the design of a FPGA Configurable Logic Block (CLB) using Asynchronous Semi-Static NULL Convention Logic (NCL) Library. The proposed design uses three semi-static LUT's for implementing NCL logic functions. Each LUT can be configured to function as any one of the 27 fundamental NCL Semi-Static gates. The proposed CLB supports 10 inputs and three different outputs, each with resettable and inverting variations. The CLB has two modes: Configuration mode and Operation mode. The Static NCL FPGA CLB is simulated at the transistor level using the 1.8V, 180nm TSMC CMOS process.

引用

页码：289 / +

页数：2

共 35 条

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