Design and implementation of FPGA configuration logic block using asynchronous semi-static NCL circuits

This paper proposes the design of a FPGA Configurable Logic Block (CLB) using Asynchronous Semi-Static NULL Convention Logic (NCL) Library. The proposed design uses three semi-static LUT's for implementing NCL logic functions. Each LUT can be configured to function as any one of the 27 fundamental NCL Semi-Static gates. The proposed CLB supports 10 inputs and three different outputs, each with resettable and inverting variations. The CLB has two modes: Configuration mode and Operation mode. The Static NCL FPGA CLB is simulated at the transistor level using the 1.8V, 180nm TSMC CMOS process.