Capacitor Scaling for Low-Power Design of Cyclic Analog-to-Digital Converters

被引：0
|
作者：
Zaare', Maryam [1 ]
Lotfi, Reza [1 ]
Maymandi-nejad, Mohammad [1 ]
机构：
[1] Ferdowsi Univ Mashhad, EE Dept, Integrated Syst Lab, Mashhad, Iran
来源：
2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS | 2010年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, in order to reduce the power consumption of a cyclic ADC, for different cycles in digitizing an analog input sample, the values of the capacitors are scaled down. The power consumption of the operational amplifier is adaptively reduced as well. In order to demonstrate the effectiveness of the proposed technique, a 1.8V 12-bit 104kS/s ADC has been designed in a 0.18 mu m CMOS technology using the modified structure and compared with conventional implementation. HSpice simulations show that applying the technique has reduced the power consumption of the ADC with a factor of more than 2.1.
引用
收藏
页码：1456 / 1459
页数：4
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