A low-power design methodology for high-resolution pipelined analog-to-digital converters

In this paper a general method to design a pipelined ADC with minimum power consumption is presented. By expressing the total static power consumption and the total input-referred noise of the converter as functions of the capacitor values and the resolutions of the converter stages, a simple optimization algorithm is employed to calculate the optimum values of these parameters, which lead to minimum power consumption while a specified noise requirement is satisfied. To determine the bias current values of operational amplifiers, a novel optimal choice for settling and slewing time parameters is proposed applicable to both single-stage and two-stage Miller-compensated opamp structures. Using the proposed methodology, the optimum values for capacitors, the resolutions and the opamp device sizes of all stages are determined in order to minimize the total power consumption. Design examples are presented and compared with conventional approaches to show the effectiveness of the proposed methodology.