Systematic design for power minimization of pipelined analog-to-digital converters

被引：0

作者：

Lotfi, R ^{[1
]}

Taherzadeh-Sani, M ^{[1
]}

Azizi, MY ^{[1
]}

Shoaei, O ^{[1
]}

机构：

[1] Univ Tehran, IC Design Lab, ECE Dept, Tehran 14174, Iran

来源：

ICCAD-2003: IEEE/ACM DIGEST OF TECHNICAL PAPERS | 2003年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper a general method to design a pipelined ADC with minimum power consumption is presented. By expressing the total power consumption and the total input-referred noise of the converter as functions of the capacitor values and the resolutions of the converter stages, an optimization algorithm is employed to calculate the optimum values of these parameters, which lead to minimum power consumption while a specific noise requirement is satisfied. To determine the bias current values of operational amplifiers an optimal choice for settling and slewing time parameters is proposed. A practical design example is presented to show the effectiveness of the proposed methodology.

引用

页码：371 / 374

页数：4

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