A time and storage optimized hardware design for context-based adaptive binary arithmetic decoding in H.264/AVC

被引：0

作者：

Zheng, Yan ^{[1
]}

Zheng, Shibao ^{[1
]}

Huang, Zhonghua ^{[1
]}

Zhao, Ziliang ^{[1
]}

机构：

[1] Shanghai Jiao Tong Univ, Inst Image Image Commun & Informat Proc, Shanghai 200240, Peoples R China

来源：

2007 IEEE INTERNATIONAL CONFERENCE ON MULTIMEDIA AND EXPO, VOLS 1-5 | 2007年

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper proposes a hardware architecture for Context-based Adaptive Binary Arithmetic Code (CABAC) decoding in H.264/AVC. The proposed architecture takes both bin decoding efficiency and control efficiency into account. This architecture improves time and storage efficiency by taking full use of the new found characters of Syntax Elements (SEs). In this architecture, two controllers are designed to decode SEs. One is the main controller, and the other is the sub controller, which controls the decoding of residual block SEs. The parallel working mode of the two controller improves the time-consuming performance of the system. Experimental result shows that our design is quite rich for main profile CIF video stream at 30fps.

引用

页码：1567 / 1570

页数：4

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