Endurance-aware RRAM-based Reconfigurable Architecture using TCAM Arrays

被引:3
|
作者
Cardoso de Lima, Joao Paulo [1 ]
Brandalero, Marcelo [2 ]
Carro, Luigi [1 ]
机构
[1] Fed Univ Rio Grande do Sul UFRGS, Informat Inst, Porto Alegre, RS, Brazil
[2] Brandenburg Univ Technol B TU, Chair Comp Engn, Cottbus, Germany
基金
欧盟地平线“2020”;
关键词
Resistive RAM; Reconfigurable architectures; Associative memory; Pattern matching; MEMORY; PERFORMANCE;
D O I
10.1109/FPL50879.2020.00018
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Field-Programmable Gate Arrays (FPGAs) have enabled the acceleration of important applications in the networking, cloud, and artificial intelligence domains while providing a flexible fabric that can be reprogrammed on demand. Still, the high static power dissipation of FPGAs driven by Static Random Access Memories (SRAMs) leads them to energy consumption levels that may be unacceptable for several application domains. Reconfigurable fabrics with emerging Resistive RAM (RRAM) technologies have been considered as one of the most promising solutions to address these energy issues of current FPGAs. However, the low endurance and the high variability of these emerging devices present a threat to the demands for reconfiguration cycles of current applications, pushing for novel architectures and design strategies techniques for improving the device's lifetime. To address these challenges, we propose a novel reconfigurable architecture targeting classes of applications that require high flexibility in the field. More specifically, we introduce a reconfigurable architecture based on Ternary Content-Addressable Memories (TCAMs) that meets a double mission: to accelerate and tolerate endurance and variation issues supported by a CAD tool that foresees the reuse of data configuration, allowing for an increased endurance in the field. We present the potential of the proposed architecture and its synthesis flow for processing Regular Expression Matching (REM), widely used in network intrusion detection systems. The results show that the performance can achieve up to 32Gbps throughput at 0.89W, while improving the device's lifetime by two orders of magnitude.
引用
收藏
页码:40 / 46
页数:7
相关论文
共 50 条
  • [41] Open-RIMC: Open-source RRAM-based IMC co-processor with reconfigurable logic mapping
    Parmar, Vivek
    Ray, Ayan
    Moorthii, Chithambara
    Mishra, Richa
    Verma, Deepak
    Pandey, Digamber
    Suri, Manan
    2023 IEEE 23RD INTERNATIONAL CONFERENCE ON NANOTECHNOLOGY, NANO, 2023, : 519 - 523
  • [42] Mitigating read-program variation and IR drop by circuit architecture in RRAM-based neural network accelerators
    Lepri, Nicola
    Glukhov, Artem
    Ielmini, Daniele
    2022 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2022,
  • [43] Monolithic three-dimensional integration of RRAM-based hybrid memory architecture for one-shot learning
    Yijun Li
    Jianshi Tang
    Bin Gao
    Jian Yao
    Anjunyi Fan
    Bonan Yan
    Yuchao Yang
    Yue Xi
    Yuankun Li
    Jiaming Li
    Wen Sun
    Yiwei Du
    Zhengwu Liu
    Qingtian Zhang
    Song Qiu
    Qingwen Li
    He Qian
    Huaqiang Wu
    Nature Communications, 14 (1)
  • [44] ESSENCE: Exploiting Structured Stochastic Gradient Pruning for Endurance-Aware ReRAM-Based In-Memory Training Systems
    Yang, Xiaoxuan
    Yang, Huanrui
    Doppa, Janardhan Rao
    Pande, Partha Pratim
    Chakrabartys, Krishnendu
    Li, Hai
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2023, 42 (07) : 2187 - 2199
  • [45] Endurance-Aware Allocation of Data Variables on NVM-Based Scratchpad Memory in Real-Time Embedded Systems
    Wang, Zhu
    Gu, Zonghua
    Yao, Min
    Shao, Zili
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2015, 34 (10) : 1600 - 1612
  • [46] Monolithic three-dimensional integration of RRAM-based hybrid memory architecture for one-shot learning
    Li, Yijun
    Tang, Jianshi
    Gao, Bin
    Yao, Jian
    Fan, Anjunyi
    Yan, Bonan
    Yang, Yuchao
    Xi, Yue
    Li, Yuankun
    Li, Jiaming
    Sun, Wen
    Du, Yiwei
    Liu, Zhengwu
    Zhang, Qingtian
    Qiu, Song
    Li, Qingwen
    Qian, He
    Wu, Huaqiang
    NATURE COMMUNICATIONS, 2023, 14 (01)
  • [47] Mitigating Read-Program Variation and IR Drop by Circuit Architecture in RRAM-Based Neural Network Accelerators
    Lepri, Nicola
    Glukhov, Artem
    Ielmini, Daniele
    2022 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2022,
  • [48] Challenges and Opportunities toward Online Training Acceleration using RRAM-based Hardware Neural Network
    Chang, Chih-Cheng
    Liu, Jen-Chieh
    Shen, Yu-Lin
    Chou, Teyuh
    Chen, Pin-Chun
    Wang, I-Ting
    Su, Chih-Chun
    Wu, Ming-Hong
    Hudec, Boris
    Chang, Che-Chia
    Tsai, Chia-Ming
    Chang, Tian-Sheuan
    Wong, H-S Philip
    Hou, Tuo-Hung
    2017 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2017,
  • [49] Energy-Efficient SNN Implementation Using RRAM-Based Computation In-Memory (CIM)
    El Arrassi, Asmae
    Gebregiorgis, Anteneh
    El Haddadi, Anass
    Hamdioui, Said
    PROCEEDINGS OF THE 2022 IFIP/IEEE 30TH INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION (VLSI-SOC), 2022,
  • [50] Bit-Aware Fault-Tolerant Hybrid Retraining and Remapping Schemes for RRAM-Based Computing-in-Memory Systems
    Huang, Yuxuan
    He, Yifan
    Wang, Jingyu
    Yue, Jinshan
    Zhang, Lu
    Zou, Kaiwei
    Yang, Huazhong
    Liu, Yongpan
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2022, 69 (07) : 3144 - 3148