Low-power SRAMs in nanoscale CMOS technologies

被引：15
|
作者：
Zhang, Kevin [1 ]
Hamzaoglu, Fatih [1 ]
Wang, Yih [1 ]
机构：
[1] Intel Corp, Hillsboro, OR 97124 USA
来源：
IEEE TRANSACTIONS ON ELECTRON DEVICES | 2008年 / 55卷 / 01期
关键词：
cache; low-power circuits; static random access memory (SRAM);
D O I：
10.1109/TED.2007.911356
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
As CMOS technology scaling is advancing beyond 100 nm, it has become increasingly difficult to meet the power and performance goals for various product applications while achieving aggressive area scaling in static random access memory (SRAM) development. This paper addresses many of the most pressing challenges in today's SRAM design from perspectives of both process technology optimization and design innovation. Key process tradeoff and optimization along with the advanced circuit design techniques for power management and low-voltage operation are discussed.
引用
收藏
页码：145 / 151
页数：7
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