Mixed-signal calibration of sample-time error in time-interleaved ADCs

被引：5
|
作者：
Zhang, P. [1 ]
Ye, F. [1 ]
Yu, B. [1 ]
Luo, L. [1 ]
Ren, J. [1 ]
机构：
[1] Fudan Univ, State Key Lab ASIC & Syst, Shanghai 200433, Peoples R China
来源：
ELECTRONICS LETTERS | 2011年 / 47卷 / 09期
关键词：
5;
D O I：
10.1049/el.2011.0547
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A mixed-signal scheme is presented to calibrate sample-time error in time-interleaved (TI) analogue-to-digital converters (ADCs). Based on the information collected by the timing error detection subsystem through digital processing, sample-time error is corrected using the proposed voltage-controlled bootstrapped switch. A two-channel TI-ADC system of 14-bit 200 MS/s has been implemented to evaluate the performance of the technique. Simulation results show that the ADC system achieves a 77.4 dB SNDR and an 84.3 dB SFDR at 97.7 MHz after calibration.
引用
收藏
页码：533 / 535
页数：3
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