Characterization and modeling of parasitic emission in deep submicron CMOS

被引：31

作者：

Vrignon, B ^{[1
]}

Bendhia, SD

Lamoureux, E

Sicard, E

机构：

[1] STMicroelect, Cent Res & Dev, F-38920 Crolles, France

[2] Inst Natl Sci Appl, F-31077 Toulouse, France

来源：

IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY | 2005年 / 47卷 / 02期

关键词：

complementary metal-oxide semiconductor (CMOS) technology; electromagnetic compatability (EMC); electromagnetic interference (EMI) modeling; on-chip sampling;

D O I：

10.1109/TEMC.2005.847408

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a study of the parasitic emissions of a 0.18-mu m CMOS experimental integrated circuit (IC) and an accurate method for modeling the internal current switching to forecast electromagnetic interference (EMI). The effectiveness of emission reduction techniques is quantified through a set of conducted noise measurements. A simple core model is developed, based on the current switching activity. Added to a lumped-element model of the test board and the package, good agreement between simulation and measurements are obtained up to 10 GHz. The simulation methodology may be applied to forecast the impact of low emission design techniques on the EMI of ICs.

引用

页码：382 / 387

页数：6

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