A new optimization cost model for VLSI standard cell placement

被引：0
|
作者：
Cheung, PYS
Yeung, CSK
Tse, SK
Yuen, CK
Ko, WL
机构：
来源：
ISCAS '97 - PROCEEDINGS OF 1997 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I - IV: CIRCUITS AND SYSTEMS IN THE INFORMATION AGE | 1997年
关键词：
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
In this paper, we propose a new optimization cost model for VLSI placement. It distinguishes itself from the traditional wire-length cost model[2][3][6] by having direct impact on the quality of the detailed routing phase, We also extend the well-known simulated annealing standard cell placement algorithm by applying our new cost model. Experimental results shows that we got 13% layout area reduction compared to traditional wire length model, 11% reduction to commercial tool.
引用
收藏
页码：1708 / 1711
页数：4
相关论文
共 50 条
  • [1] A new optimization model for VLSI placement algorithms
    Cheung, PYS
    Yeung, CSK
    Ko, RWL
    ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 6: CIRCUITS ANALYSIS, DESIGN METHODS, AND APPLICATIONS, 1999, : 398 - +
  • [2] A Nonlinear Analytical Optimization Method for Standard Cell Placement of VLSI Circuits
    Pawanekar, Sameer
    Trivedi, Gaurav
    Kapoor, Kalpesh
    2015 28TH INTERNATIONAL CONFERENCE ON VLSI DESIGN (VLSID), 2015, : 423 - 428
  • [3] Optimization of Hybrid and Local Search Algorithms for Standard Cell Placement in VLSI Design
    Bunglowala, Aaqull
    Singhi, B. M.
    Verma, Ajay
    2009 INTERNATIONAL CONFERENCE ON ADVANCES IN RECENT TECHNOLOGIES IN COMMUNICATION AND COMPUTING (ARTCOM 2009), 2009, : 826 - +
  • [4] An Analytical Placer for VLSI Standard Cell Placement
    Chen, Jianli
    Zhu, Wenxing
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2012, 31 (08) : 1208 - 1221
  • [5] Congestion driven placement for VLSI standard cell design
    Areibi, S
    Yang, Z
    ICM 2003: PROCEEDINGS OF THE 15TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS, 2003, : 304 - 307
  • [6] Optimization of Cost Function with Cell Library placement of VLSI circuits using Simulated Annealing
    Khorgade, Manisha
    Deshmukh, A. Y.
    Bajaj, Preeti
    Keskar, A. G.
    2009 SECOND INTERNATIONAL CONFERENCE ON EMERGING TRENDS IN ENGINEERING AND TECHNOLOGY (ICETET 2009), 2009, : 699 - 704
  • [7] Iterative heuristics for multiobjective VLSI standard cell placement
    Sait, SM
    Youssef, H
    El-Maleh, AH
    Minhas, MR
    IJCNN'01: INTERNATIONAL JOINT CONFERENCE ON NEURAL NETWORKS, VOLS 1-4, PROCEEDINGS, 2001, : 2224 - 2229
  • [8] A PROCEDURE FOR PLACEMENT OF STANDARD-CELL VLSI CIRCUITS
    DUNLOP, AE
    KERNIGHAN, BW
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1985, 4 (01) : 92 - 98
  • [9] A hierarchical standard cell placement method based on a new cluster placement model
    Wakabayashi, S
    Iwauchi, N
    Kubota, H
    APCCAS 2002: ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, VOL 1, PROCEEDINGS, 2002, : 273 - 278
  • [10] An Adaptive Hybrid Genetic Algorithm for VLSI Standard Cell Placement Problem
    Chen, Xiongfeng
    Lin, Geng
    Chen, Jianli
    Zhu, Wenxing
    2016 3RD INTERNATIONAL CONFERENCE ON INFORMATION SCIENCE AND CONTROL ENGINEERING (ICISCE), 2016, : 163 - 167
12345