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- [1] Ultra-Thin and Ultra-high I/O Density Package-on-Package (3D Thin PoP) for High Bandwidth of Smart Systems 2013 IEEE 63RD ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2013, : 406 - 411
- [2] Sea of Leads ultra high-density compliant wafer-level packaging technology 52ND ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, 2002 PROCEEDINGS, 2002, : 1087 - 1094
- [3] Low cost flip chip package design concepts for high density I/O 51ST ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, 2001, : 1140 - 1143
- [4] A ceramic pin grid array package with 370 I/O leads FIFTH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY, PROCEEDINGS, 2003, : 115 - 116
- [5] Development on Ultra High Density Memory Package with PoP Structure 2011 IEEE 61ST ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2011, : 1136 - 1140
- [7] Compliant wafer level package (CWLP) with embedded air-gaps for Sea of Leads (SoL) interconnections PROCEEDINGS OF THE IEEE 2001 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2001, : 151 - 153
- [8] Ultra High Density Package Design and Electrical Analysis in High Performance Computing Application 2019 IEEE 21ST ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC), 2019, : 457 - 460
- [9] Ultra-high I/O Density Glass/Silicon Interposers for High Bandwidth Smart Mobile Applications 2011 IEEE 61ST ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2011, : 217 - 223
- [10] Fine line photolithography and ultra high density package substrate for next generation system-on-package (SOP) ICEPT: 2007 8TH INTERNATIONAL CONFERENCE ON ELECTRONICS PACKAGING TECHNOLOGY, PROCEEDINGS, 2007, : 109 - 113