A Scan Cell Architecture for Inter-Clock At-Speed Delay Testing

被引：0
|
作者：
Cho, Kyoung Youn [1 ]
Srinivasan, Rajagopalan [1 ]
机构：
[1] NVIDIA, Santa Clara, CA 95050 USA
来源：
2011 IEEE 29TH VLSI TEST SYMPOSIUM (VTS) | 2011年
关键词：
design for testability (DFT); scan cell architecture; delay testing; at-speed testing; inter-clock logic; DESIGNS;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
At-speed delay testing is inevitable for improving the test quality of modern high-speed semiconductor chips. This paper presents a scan cell architecture for at-speed testing of delay faults in inter-clock logic. The technique utilizes commercially available ATPG tools for test pattern generation and internal PLL clocks for test pattern application. The hardware modification is contained within the scan cells and no additional global routing is required. Simulation results using three industrial designs demonstrate that the technique is effective in detecting delay faults in inter-clock logic.
引用
收藏
页码：213 / 218
页数：6
相关论文
共 50 条
  • [31] A simulator for at-speed robust testing of path delay faults in combinational circuits
    Hsu, YC
    Gupta, SK
    IEEE TRANSACTIONS ON COMPUTERS, 1996, 45 (11) : 1312 - 1318
  • [32] At-speed boundary-scan interconnect testing in a board with multiple system clocks
    Shin, J
    Kim, H
    Kang, S
    DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION 1999, PROCEEDINGS, 1999, : 473 - 477
  • [33] Development of an ATE Test Cell for At-Speed Characterization and Production Testing
    Moreira, Jose
    2011 IEEE INTERNATIONAL TEST CONFERENCE (ITC), 2011,
  • [34] Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch
    Asada, K.
    Wen, X.
    Holst, S.
    Miyase, K.
    Kajihara, S.
    Kochte, M. A.
    Schneider, E.
    Wunderlich, H. -J.
    Qian, J.
    2015 IEEE 24TH ASIAN TEST SYMPOSIUM (ATS), 2015, : 103 - 108
  • [35] Power-Aware Test Generation with Guaranteed Launch Safety for At-Speed Scan Testing
    Wen, X.
    Enokimoto, K.
    Miyase, K.
    Yamato, Y.
    Kochte, M. A.
    Kajihara, S.
    Girard, P.
    Tehranipoor, M.
    2011 IEEE 29TH VLSI TEST SYMPOSIUM (VTS), 2011, : 166 - 171
  • [36] CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing
    Furukawa, H.
    Wen, X.
    Miyase, K.
    Yamato, Y.
    Kajihara, S.
    Girard, P.
    Wang, L. -T.
    Tehranipoor, M.
    PROCEEDINGS OF THE 17TH ASIAN TEST SYMPOSIUM, 2008, : 397 - +
  • [37] Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression Environment
    Wu, Meng-Fan
    Huang, Jiun-Lang
    Wen, Xiaoqing
    Miyase, Kohei
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2009, 28 (11) : 1767 - 1776
  • [38] Low Cost At-Speed Testing using On-Product Clock Generation Compatible with Test Compression
    Keller, B.
    Chakravadhanula, K.
    Foutz, B.
    Chickermane, V.
    Malneedi, R.
    Snethen, T.
    Iyengar, V.
    Lackey, D.
    Grise, G.
    INTERNATIONAL TEST CONFERENCE 2010, 2010,
  • [39] At-speed testing of delay faults for motorola's MPC7400, a powerPC microprocessor
    Tendolkar, Nandu
    Molyneaux, Robert
    Proceedings of the IEEE VLSI Test Symposium, 2000, : 3 - 8
  • [40] Capture-Power-Safe Test Pattern Determination for At-Speed Scan-Based Testing
    Li, Yi-Hua
    Lien, Wei-Cheng
    Lin, Ing-Chao
    Lee, Kuen-Jong
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2014, 33 (01) : 127 - 138
12345