At-speed testing of delay faults for motorola's MPC7400, a powerPC microprocessor

被引：0

作者：

Tendolkar, Nandu ^{[1
]}

Molyneaux, Robert ^{[1
]}

机构：

[1] Motorola, Inc, Austin, United States

来源：

Proceedings of the IEEE VLSI Test Symposium | 2000年

关键词：

Integrated circuit layout - Integrated circuit testing - Microprocessor chips - Response time (computer systems) - Timing circuits;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

In this paper we present the novel built-in delay fault test concepts incorporated into Motorola's MPC7400 PowerPC microprocessor that allow us to use a slow speed tester to do at-speed, scan based, delay fault testing. A novel feature of the design is the programmable clock control circuit of issuing a given number of at-speed clocks for the delay test, once the test is initiated. Using transition and path delay fault test patterns, we have tested several MPC7400 chips at speed exceeding 540 MHz using tester speed of 63 MHz or lower.

引用

页码：3 / 8

共 22 条

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