Novel techniques for achieving high at-speed transition fault test coverage for Motorola's microprocessors based on PowerPC™ instruction set architecture

被引：0

作者：

Tendolkar, N ^{[1
]}

Raina, R ^{[1
]}

Woltenberg, R ^{[1
]}

Lin, XJ ^{[1
]}

Swanson, B ^{[1
]}

Aldrich, G ^{[1
]}

机构：

[1] Motorola Inc, Austin, TX 78727 USA

来源：

20TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS | 2002年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Scan based at-speed transition fault testing of Motorola's microprocessors based on the PowerPC(TM) instruction set architecture requires broad-side transition fault test patterns that have a specific launch and capture clocking sequence. We describe the concepts we developed and incorporated in the ATPG tool to support efficient generation of such test patterns to achieve high transition fault test coverage and for analysis of undetected transition faults. Using the enhanced ATPG tool, we generated 15,000 transition fault test patterns and achieved 76% test coverage for the MPC7400 microprocessor based on the PowerPC(TM) instruction set architecture that has 10.5 million transistors and runs at 540 MHz.

引用

页码：3 / 8

页数：6