On diagnosing path delay faults in an at-speed environment

被引：9

作者：

Tekumalla, RC ^{[1
]}

Venkataraman, S ^{[1
]}

Ghosh-Dastidar, J ^{[1
]}

机构：

[1] Intel Corp, Hillsboro, OR 97124 USA

来源：

19TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS | 2001年

关键词：

D O I：

10.1109/VTS.2001.923414

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

Recent techniques for path delay fault diagnosis have addressed the problem in combinational circuits and sequential circuits. The root cause of a path delay fault test failure is narrowed down to a set of functionally sensitized paths and this set is further reduced by post processing the set of passing tests. In this paper; we present a method for narrowing down the suspects further to a set of segments on the failing functionally sensitized paths. The proposed method is implemented and applied to a set of industrial circuits and it is found to be very effective in determining the defective segments that explain excessive delays along paths.

引用

页码：28 / 33

页数：6

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