A multiplexer based test method for self-timed circuits

被引:0
|
作者
te Beest, F [1 ]
Peeters, A [1 ]
机构
[1] Philips Technol Incubator, Handshake Solut, Eindhoven, Netherlands
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
A new test method for self-timed circuits is presented that only uses multiplexers to make the majority of combinational feedback loops testable. Combinational feedback loops are problematic for testing, since they introduce sequential behavior in a circuit. Traditionally feedback loops are broken with scan latches or even scan flip-flops, which causes not only a large area overhead, but also have a large impact on performance. The method we present significantly reduces the cost of testing a self-timed circuit, while it retains all the benefits of traditional scan test methods. Most importantly, the method remains fully compatible with standard combinational test pattern generation tools and provides up to 100% stuck-at-fault coverage. With the presented test method it becomes cost effective to use scan test for a self-timed circuit without the need to add new specialized cells to a standard cell library.
引用
下载
收藏
页码:166 / 175
页数:10
相关论文
共 50 条
  • [1] Towards Hazard-Free Multiplexer Based Implementation of Self-Timed Circuits
    Kushnerov, Alexander
    Medina, Moti
    Yakovlev, Alexandre
    27TH IEEE INTERNATIONAL SYMPOSIUM ON ASYNCHRONOUS CIRCUITS AND SYSTEMS (ASYNC 2021), 2021, : 17 - 24
  • [3] Prototype board for the test of self-timed circuits developed in FPGAs
    Raya, MS
    Naharro, RJ
    Ramírez, JC
    VLSI CIRCUITS AND SYSTEMS II, PTS 1 AND 2, 2005, 5837 : 1039 - 1046
  • [4] Improving SRAM Test Quality by Leveraging Self-timed Circuits
    Kinseher, Josef
    Zordan, Leonardo B.
    Polian, Ilia
    Leininger, Andreas
    PROCEEDINGS OF THE 2016 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2016, : 984 - 989
  • [5] Rapid prototyping of self-timed circuits
    Moore, SW
    Robinson, P
    INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS, 1998, : 360 - 365
  • [6] Specification and analysis of self-timed circuits
    Kishinevsky, M.A.
    Kondratyev, A.Y.U.
    Taubin, A.R.
    Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, 1994, 7 (1-2): : 117 - 135
  • [7] An investigation into the security of self-timed circuits
    Yu, ZC
    Furber, SB
    Plana, LA
    NINTH INTERNATIONAL SYMPOSIUM ON ASYNCHRONOUS CIRCUITS AND SYSTEMS, PROCEEDINGS, 2003, : 206 - 215
  • [8] SELF-TIMED LOGIC-CIRCUITS
    POOLE, NR
    ELECTRONICS & COMMUNICATION ENGINEERING JOURNAL, 1994, 6 (06): : 261 - 270
  • [9] Performance optimization of self-timed circuits
    Franklin, MA
    Prabhu, P
    PROCEEDINGS OF THE 8TH GREAT LAKES SYMPOSIUM ON VLSI, 1998, : 374 - 379
  • [10] Optimising Self-timed FPGA circuits
    Ferguson, Phillip David
    Efthymiou, Aristides
    Arslan, Tughrul
    Hume, Danny
    13TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN: ARCHITECTURES, METHODS AND TOOLS, 2010, : 563 - 570