The influence and explanation of fringing-induced barrier lowering on sub-100 nm MOSFETs with high-k gate dielectrics

被引：6

作者：

Ma Fei ^{[1
]}

Liu Hong-Xia ^{[1
]}

Kuang Qian-Wei ^{[1
]}

Fan Ji-Bin ^{[1
]}

机构：

[1] Xidian Univ, Sch Microelect, Key Lab, Minist Educ Wide Band Gap Semicond Mat & Devices, Xian 710071, Peoples R China

来源：

CHINESE PHYSICS B | 2012年 / 21卷 / 05期

基金：

中国国家自然科学基金;

关键词：

high-k gate dielectric; fringing-induced barrier lowering; stack gate dielectric; MOSFET; THRESHOLD VOLTAGE MODEL; SOI-MOSFET; FIBL; PERFORMANCE; IMPACT;

D O I：

10.1088/1674-1056/21/5/057305

中图分类号：

O4 [物理学];

学科分类号：

0702 ;

摘要：

The fringing-induced barrier lowering (FIBL) effect of sub-100 nm MOSFETs with high-k gate dielectrics is investigated using a two-dimensional device simulator. An equivalent capacitance theory is proposed to explain the physics mechanism of the FIBL effect. The FIBL effect is enhanced and the short channel performance is degraded with increasing capacitance. Based on equivalent capacitance theory, the influences of channel length, junction depth, gate/lightly doped drain (LDD) overlap length, spacer material and spacer width on FIBL is thoroughly investigated. A stack gate dielectric is presented to suppress the FIBL effect.

引用

页数：5

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