Design and implementation of multi-channel high speed HDLC data processor

被引：0
|
作者：
Lu, YL [1 ]
Wang, ZG [1 ]
Qiao, LF [1 ]
Huang, B [1 ]
机构：
[1] Southeast Univ, Inst RF & OE ICs, Nanjing 210096, Peoples R China
来源：
2002 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS AND WEST SINO EXPOSITION PROCEEDINGS, VOLS 1-4 | 2002年
关键词：
HDLC; communication protocol; time-multiplex; FPGA;
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
This paper presents the design of a multi-channel high speed HDLC data processor that can processes 128 logic channel HDLC data simultaneously. Its logic function and communication protocol coherence has been verified successfully by a real-time operation system-VxWorks through FPGA. In the system, this multi-channel HDLC processor connects with 8 E1 physical links, and all 128 logic channel data separated from 256 timeslots of 8 E1 frames are processed by this single HDLC processor by using time multiplex technology. Compared with other communication chips of the similar type, this circuit structure takes more advantages in chip resources' taking up and channel management.
引用
收藏
页码：1471 / 1475
页数：5
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