Development of InGaAs-based multiple-junction surface tunnel transistors for multiple-valued logic circuits

被引：11
|
作者：
Baba, T [1 ]
Uemura, T [1 ]
机构：
[1] NEC Corp Ltd, Fundamental Res Labs, Tsukuba, Ibaraki 305, Japan
来源：
1998 28TH IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC - PROCEEDINGS | 1998年
关键词：
D O I：
10.1109/ISMVL.1998.679267
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Multiple negative-differential-resistance (NDR) characteristics (up to six NDRs) are demonstrated by fabricating multiple-junction surface tunnel transistors (MJ-ST;rs) using an InGaAs material system. The tunneling current density is 500 times larger than that for a GaAs-based MJ-STT as well as higher peak-to-valley ratios (about 5). As an application of MJ-STTs for binary and multiple-valued logic, a programmable NAND/NOR logic circuit and a three-valued inverter circuit are implemented monolithically. Proper circuit operations of these circuits are confirmed using an oscillatory supply voltage.
引用
收藏
页码：7 / 12
页数：6
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