Increased hot carrier effects in Gate-All-Around SOI nMOSFET's

被引：3
|
作者：
Park, JT
Choi, NJ
Yu, CG
Jeon, SH
Colinge, JP
机构：
[1] Univ Inchon, Dept Elect Engn, Inchon 402749, South Korea
[2] Univ Calif Davis, Dept Elect & Comp Engn, Davis, CA 95616 USA
来源：
MICROELECTRONICS RELIABILITY | 2003年 / 43卷 / 9-11期
关键词：
D O I：
10.1016/S0026-2714(03)00254-3
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Increased device degradation due to hot-electron effects in Gate-All-Around (GAA) SOI nMOSFETs is investigated. The most significant degradation takes place in the parasitic parasitic transistor, which is the weakest region with regard to impact ionization. The condition of V(GS)congruent toV(TH) is shown to be the worst-case device degradation as in FD SOI devices. Degradation rate and dynamic transconductance measurements show that interface state generation is responsible for device degradation. The higher generation rate at the edge of devices is confirmed from the larger degradation observed in multi-finger gate devices. (C) 2003 Elsevier Ltd. All rights reserved.
引用
收藏
页码：1427 / 1432
页数：6
相关论文
共 50 条
  • [21] Corner effects in double-gate/gate-all-around MOSFETs
    Hou Xiao-Yu
    Zhou Fa-Long
    Huang Ru
    Zhang Xing
    CHINESE PHYSICS, 2007, 16 (03): : 812 - 816
  • [22] A method for the prediction of hot-carrier lifetime in floating SOI NMOSFET's
    Maeda, S
    Yamaguchi, Y
    Kim, IJ
    Joachim, HO
    Inoue, Y
    Miyoshi, H
    Yasuoka, A
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 1997, 44 (12) : 2200 - 2206
  • [23] On and off state Hot Carrier reliability in Junctionless high-K MG gate-all-around nanowires
    Cho, M.
    Heflings, G.
    Vcloso, A.
    Simocn, E.
    Roussel, Ph.
    Kaczcr, B.
    Arimura, H.
    Fang, W.
    Franco, J.
    Matagne, P.
    Colbert, N.
    Linten, D.
    Thean, A.
    2015 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2015,
  • [24] Modeling and parameter extraction of gate-all-around nMOS/SOI transistors in the linear region
    Chang, YS
    Li, SS
    SOLID-STATE ELECTRONICS, 1996, 39 (07) : 991 - 997
  • [25] EVIDENCE OF 2-DIMENSIONAL CARRIER CONFINEMENT IN THIN N-CHANNEL SOI GATE-ALL-AROUND (GAA) DEVICES
    COLINGE, JP
    BAIE, X
    BAYOT, V
    IEEE ELECTRON DEVICE LETTERS, 1994, 15 (06) : 193 - 195
  • [26] Gate-all-around Ge FETs
    Liu, C. W.
    Chen, Y. -T.
    Hsu, S. -H.
    SIGE, GE, AND RELATED COMPOUNDS 6: MATERIALS, PROCESSING, AND DEVICES, 2014, 64 (06): : 317 - 328
  • [27] Structure effects in the gate-all-around silicon nanowire MOSFETs
    Liang, Gengchiau
    EDSSC: 2007 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS, VOLS 1 AND 2, PROCEEDINGS, 2007, : 129 - 132
  • [28] Investigation of hot carrier effects in SOI nMOSFET's operating in a Bi-MOS mode with mesa isolation
    Huang, R
    Hang, Y
    He, J
    Wang, YY
    SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1 AND 2, PROCEEDINGS, 2001, : 661 - 664
  • [29] Characterization of Gate-All-Around Si-NWFET, including Rsd, Cylindrical Coordinate Based 1/f Noise and Hot Carrier Effects
    Baek, Rock-Hyun
    Choi, Hyun-Sik
    Sagong, Hyun Chul
    Lee, Sang-Hyun
    Choi, Gil-Bok
    Song, Seung Hyun
    Park, Chan-Hoon
    Lee, Jeong-Soo
    Jeong, Yoon-Ha
    Baek, Chang-Ki
    Kim, Dae Mann
    2010 INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, 2010, : 94 - 98
  • [30] Fast and efficient light intensity modulation in SOI with gate-all-around transistor phase modulator
    Dainesi, P
    Moselund, KE
    Thévenaz, L
    Ionescu, AM
    2005 Conference on Lasers & Electro-Optics (CLEO), Vols 1-3, 2005, : 110 - 112
12345