High Thermal Graphite TIM Solution Applied to Fan-Out Platform

被引:3
|
作者
Su, Pin-Jing [1 ]
Lin, Dan [1 ]
Lin, Shane [1 ]
Xu, Xi-Zhang [1 ]
Lin, Rung Jeng [1 ]
Hung, Liang-Yih [1 ]
Wang, Yu-Po [1 ]
机构
[1] Siliconware Precis Ind Co Ltd SPIL, Corp R&D, Taichung, Taiwan
关键词
HPC; Fan-out; Graphite TIM; Vertical Thermal Conductivity;
D O I
10.1109/ECTC51906.2022.00196
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In the 5G era, the high performance computing (HPC) products play a pivotal role in supporting big data computing, data center transmission and networking applications. For computing performance enhancement, there are two development trends of product design including chip integration and high thermal dissipation. First, integrating the high bandwidth memory (HBM) into the package is a way to achieve both short and high-speed data transmission. In industry, fan-out platform can provide the benefit for die to die interconnection with fine line and the fine pitch bump design. Second, HPC devices bring high power consumption and require a thermal interface material (TIM) with high thermal conductivity for junction temperature reduction of SoC chip, due to the higher junction temperature will have work fail risk of SoC and even affect the nearby HBM. For high thermal TIM, the thermal conductivity of graphite TIM is directional, XY and Z axis are around 10W/mK and 20W/mK, respectively. The heat dissipation are not only through the vertical direction but also partially through the horizontal direction to the surroundings. The outstanding vertical thermal conductivity can effectively reduce the heat from SoC hot spot and reduce the thermal impact on HBM. Compared with normal FCBGA platform, a way to evaluate graphite TIM in FO structure is provided in this study. The maximum junction temperature impact of SoC and HBM is being explored from thermal simulation between different SoC hot spot design including uniform, center and corner conditions. In addition, the top exposed surface of chip module includes multiple interface with silicon and epoxy molding compound (EMC). We address the graphite TIM attaching performance and TIM coverage. Furthermore, through the innovative structure design to add the adhesive around the chip module, TIM coverage can be improved, especially for large package with worse warpage. All of the silicon die, EMC and underfill are pass without crack from SEM inspection, even if a larger HS (Heat Spreader) clamping force is required for graphite TIM. Finally, we have finished and passed the PLR (Package Level Reliability) with temperature cycle test (TCT) and unbiased highly accelerated stress test (uHAST) conditions.
引用
收藏
页码:1224 / 1227
页数:4
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