High-Accuracy Fixed-Width Booth Multipliers Based on Probability and Simulation

被引：13

作者：

He, Wen-Quan ^{[1
,2
]}

Chen, Yuan-Ho ^{[3
]}

Jou, Shyh-Jye ^{[1
,2
]}

机构：

[1] Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu 300, Taiwan

[2] Natl Chiao Tung Univ, Inst Elect, Hsinchu 300, Taiwan

[3] Chang Gung Univ, Dept Elect Engn, Taoyuan 333, Taiwan

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | 2015年 / 62卷 / 08期

关键词：

Booth encoder; dynamic error-compensation; fixed-width multiplier; mathematical probable model; LOW-ERROR; DCT APPLICATIONS; ESTIMATION BIAS; COMPENSATION; CIRCUITS;

D O I：

10.1109/TCSI.2015.2440731

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This study developed a high accuracy dynamic error-compensation circuit for fixed-width Booth multipliers based on probability and computer simulation (PACS). PACS begins by generating several potential solutions based on both conditional and expected probability, whereupon the accuracy of the solutions is verified using computer simulation and the solution with the highest accuracy is selected. In addition to being highly accurate, the proposed PACS approach is area-effective. This study used the TSMC 0.18-mu m CMOS to fabricate a 16-bit Booth multiplier with an operating frequency of 100 MHz and power consumption of 6.7 mW.

引用

页码：2052 / 2061

页数：10

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