40nm CMOS 0.35V-Optimized Standard Cell Libraries for Ultra-Low Power Applications

被引：3

作者：

Abouzeid, Fady ^{[1
]}

Clerc, Sylvain ^{[1
]}

Firmin, Fabian ^{[1
]}

Renaudin, Marc

Sas, Tiempo

Sicard, Gilles

机构：

[1] STMicroelectronics, F-38920 Crolles, France

来源：

ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS | 2011年 / 16卷 / 03期

关键词：

Design; Experimentation; Measurement; Performance; Reliability; Verification; Bose Choudhury Hocquenghem; CMOS; circuit; design; energy; library; logic; low power; methodology; subthreshold; ultra low voltage; SUBTHRESHOLD LOGIC; ENERGY;

D O I：

10.1145/1970353.1970369

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Ultra-low voltage is now a well-known solution for energy constrained applications designed using nanometric process technologies. This work is focused on setting up an automated methodology to enable the design of ultra-low voltage digital circuits exclusively using standard EDA tools. To achieve this goal, a 0.35V energy-delay optimized library was developed. This library, fully compliant with standard library design flow and characterization, was verified through the design and fabrication of a BCH decoder circuit, following a standard front-end to back-end flow. At 0.33V, it performs at 600 kHz with a dynamic energy consumption reduced by a factor 14x from nominal 1.1V. Based on this design, experiments, and preliminary silicon results, two additional libraries were developed in order to enhance future ultra-low voltage circuit performance.

引用

页数：17

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