Optimizing circuit performance and ESD protection for high-speed differential I/Os

被引：8

作者：

Sarbishaei, H. ^{[1
]}

Semenov, O. ^{[1
]}

Sachdev, M. ^{[1
]}

机构：

[1] Univ Waterloo, Dept Elect & Comp Engn, Waterloo, ON N2L 3G1, Canada

来源：

PROCEEDINGS OF THE IEEE 2007 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2007年

关键词：

D O I：

10.1109/CICC.2007.4405701

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Impact of ESD protection devices on circuit operation is very important in gigahertz applications. In this paper, the impact of different ESD protection methodologies on CML drivers is discussed. ESD protection is provided using MOSFET and SCR devices. Study of the interaction between driver and ESD protection circuit shows that jitter is very sensitive to parasitics of ESD protection circuits. Furthermore, an analysis shows that substrate- triggering has less impact on jitter compared to gate-coupling.

引用

页码：149 / 152

页数：4

共 50 条

[41] ESD Protection Design for VBO-based High-speed Multimedia Interface Chip
Li, Xiang
Dong, Shurong
Hu, Tao
2017 IEEE 24TH INTERNATIONAL SYMPOSIUM ON THE PHYSICAL AND FAILURE ANALYSIS OF INTEGRATED CIRCUITS (IPFA), 2017,
[42] High-Speed Differential Protection for Smart DC Distribution Systems
Fletcher, Steven D. A.
Norman, Patrick J.
Fong, Kenny
Galloway, Stuart J.
Burt, Graeme M.
IEEE TRANSACTIONS ON SMART GRID, 2014, 5 (05) : 2610 - 2617
[43] High-Speed TLP and ESD Characterization of ICs
Muhonen, Kathleen
Grund, Evan
Ashton, Robert
2021 IEEE BICMOS AND COMPOUND SEMICONDUCTOR INTEGRATED CIRCUITS AND TECHNOLOGY SYMPOSIUM (BCICTS), 2021,
[44] Evaluating high-speed ESD suppression technologies
Schroeder, Kory
Electronic Products (Garden City, New York), 2010, 52 (10):
[45] HIGH-SPEED COMPARISON CIRCUIT
TSOKANOV, VV
INSTRUMENTS AND EXPERIMENTAL TECHNIQUES-USSR, 1967, (04): : 902 - &
[46] A high-speed median circuit
Opris, IE
Kovacs, GTA
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1997, 32 (06) : 905 - 908
[47] A FULLY DIFFERENTIAL SAMPLE-AND-HOLD CIRCUIT FOR HIGH-SPEED APPLICATIONS
NICOLLINI, G
CONFALONIERI, P
SENDEROWICZ, D
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1989, 24 (05) : 1461 - 1465
[48] ESD protection design for giga-Hz high-speed I/O interfaces in a 130-nm CMOS process
Hsiao, Yuan-Wen
Ker, Ming-Dou
Chiu, Po-Yen
Huang, Chun
Tseng, Yuh-Kuang
20TH ANNIVERSARY IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS, 2007, : 277 - +
[49] Low-capacitance ESD protection design for high-speed I/O interfaces in a 130-nm CMOS process
Hsiao, Yuan-Wen
Ker, Ming-Dou
MICROELECTRONICS RELIABILITY, 2009, 49 (06) : 650 - 659
[50] ESD Self-Protection of High-Speed Transceivers Using Adaptive Active Bias Conditioning
Keel, Min-Sun
Rosenbaum, Elyse
IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2017, 17 (01) : 113 - 120

← 1 2 3 4 5 →