Optimizing circuit performance and ESD protection for high-speed differential I/Os

被引：8

作者：

Sarbishaei, H. ^{[1
]}

Semenov, O. ^{[1
]}

Sachdev, M. ^{[1
]}

机构：

[1] Univ Waterloo, Dept Elect & Comp Engn, Waterloo, ON N2L 3G1, Canada

来源：

PROCEEDINGS OF THE IEEE 2007 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2007年

关键词：

D O I：

10.1109/CICC.2007.4405701

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Impact of ESD protection devices on circuit operation is very important in gigahertz applications. In this paper, the impact of different ESD protection methodologies on CML drivers is discussed. ESD protection is provided using MOSFET and SCR devices. Study of the interaction between driver and ESD protection circuit shows that jitter is very sensitive to parasitics of ESD protection circuits. Furthermore, an analysis shows that substrate- triggering has less impact on jitter compared to gate-coupling.

引用

页码：149 / 152

页数：4

共 50 条

[21] A new ESD protection structure for high-speed GaAs RF ICs
Sun, MY
Lu, YC
IEEE ELECTRON DEVICE LETTERS, 2005, 26 (03) : 133 - 135
[22] Modeling and analysis of OS performance in high-speed networks
Salah, K
El-Badawi, K
CIC'03: PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON COMMUNICATIONS IN COMPUTING, 2003, : 249 - 255
[23] Resistor-Triggered SCR Device for ESD Protection in High-Speed I/O Interface Circuits
Lin, Chun-Yu
Chen, Chun-Yu
IEEE ELECTRON DEVICE LETTERS, 2017, 38 (06) : 712 - 715
[24] Layout Optimization of ESD Protection Diodes for High-Frequency I/Os
Bhatia, Karan
Jack, Nathan
Rosenbaum, Elyse
IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2009, 9 (03) : 465 - 475
[25] ESTIMATING HIGH-SPEED CIRCUIT INTERCONNECT PERFORMANCE
SAINATI, RA
MORAVEC, TJ
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, 1989, 36 (04): : 533 - 541
[26] RF/High-Speed I/O ESD Protection: Co-optimizing Strategy Between BEOL Capacitance and HBM Immunity in Advanced CMOS Process
Son, Dokyun
Park, Jaeyeol
Shin, Hyungcheol
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2020, 67 (07) : 2778 - 2784
[27] High-speed interface circuit for differential capacitance transducers
Kim, Hoon
Rho, Il-Ho
Chung, Won-Sup
IEICE ELECTRONICS EXPRESS, 2011, 8 (02): : 96 - 102
[28] Power-centric design of high-speed I/Os
Hatamkhani, Hamid
Lambrecht, Frank
Stojanovic, Vladimir
Yang, Chih-Kong Ken
43RD DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2006, 2006, : 867 - +
[29] A fail-safe ESD protection circuit with 230 fF linear capacitance for high-speed/high-precision 0.18 μm CMOS I/O application
Lin, J
Duvvury, C
Haroun, B
Oguzman, I
Somayaji, A
INTERNATIONAL ELECTRON DEVICES 2002 MEETING, TECHNICAL DIGEST, 2002, : 349 - 352
[30] APPLICATION CRITERIA FOR HIGH-SPEED BUS DIFFERENTIAL PROTECTION
CABLE, BW
POWELL, LJ
SMITH, RL
IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, 1983, 19 (04) : 619 - 624

← 1 2 3 4 5 →