LETAM: A low energy truncation-based approximate multiplier

被引:32
|
作者
Vahdat, Shaghayegh [1 ]
Kamal, Mehdi [1 ,2 ]
Afzali-Kusha, Ali [1 ]
Pedram, Massoud [3 ]
机构
[1] Univ Tehran, Sch Elect & Comp Engn, Tehran, Iran
[2] Inst Res Fundamental Sci, Sch Comp Sci, Tehran, Iran
[3] Univ Southern Calif, Dept Elect Engn, Los Angeles, CA 90089 USA
基金
美国国家科学基金会;
关键词
Approximate multiplier; Truncating; Low power; Energy efficient; JPEG encoder; BINARY LOGARITHMS;
D O I
10.1016/j.compeleceng.2017.08.019
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In this paper, we propose an energy efficient approximate multiplier design obtained by truncating the input operands. In the structure, the n-bit multiplication operation is transformed to a smaller bit length multiplication plus some add and shift operations. The simple calculation core makes the multiplier a scalable yet low power structure. Also, we suggest an output quality-tunable multiplier providing ability to change the output quality during the multiplication operation. The characteristics of the proposed multiplier are compared with those of the exact and some other approximate multipliers in a 45 nm technology. The comparison reveals an average improvement of 89.2% (74.9%) in terms of the energy (area) compared to that of the exact multiplier. The utility of the proposed multiplier in a JPEG encoder application is also investigated. The results reveal that the Peak Signal to Noise Ratio (PSNR) reduction is at most 0.15 dB compared to that of the exact one. (C) 2017 Elsevier Ltd. All rights reserved.
引用
收藏
页码:1 / 17
页数:17
相关论文
共 50 条
  • [21] An Energy Efficient 32 Bit Approximate Dadda Multiplier
    Chanda, Saurav
    Guha, Koushik
    Patra, Santu
    Singh, Loukrakpam Merin
    Baishnab, Krishna Lal
    Paul, Prashanta Kumar
    2020 IEEE CALCUTTA CONFERENCE (CALCON), 2020, : 162 - 165
  • [22] Energy Efficient Approximate Multiplier for Image Processing Applications
    Chakraborty, Adrija
    Kumar, Vishal Pranao Amarnath
    Vruddhula, Akash Kumar
    Naidu, K. Jagannadha
    Balamurugan, S.
    RESULTS IN ENGINEERING, 2025, 25
  • [23] Approximate digital-in analog-out multiplier with asymmetric nonvolatility and low energy consumption
    Yu, Shengqi
    Xia, Fei
    Shafik, Rishad
    Balsamo, Domenico
    Yakovlev, Alex
    INTEGRATION-THE VLSI JOURNAL, 2023, 93
  • [24] Memristor-based approximate matrix multiplier
    Mohsen Nourazar
    Vahid Rashtchi
    Ali Azarpeyvand
    Farshad Merrikh-Bayat
    Analog Integrated Circuits and Signal Processing, 2017, 93 : 363 - 373
  • [25] Memristor-based approximate matrix multiplier
    Nourazar, Mohsen
    Rashtchi, Vahid
    Azarpeyvand, Ali
    Merrikh-Bayat, Farshad
    ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2017, 93 (02) : 363 - 373
  • [26] Design of a Low-Cost Approximate Adder with a Zero Truncation
    Lee, Jungwon
    Seo, Hyoju
    Kim, Yerin
    Kim, Yongtae
    2020 17TH INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC 2020), 2020, : 69 - 70
  • [27] A Novel Heterogeneous Approximate Multiplier for Low Power and High Performance
    Alouani, Ihsen
    Ahangari, Hamzeh
    Ozturk, Ozcan
    Niar, Smail
    IEEE EMBEDDED SYSTEMS LETTERS, 2018, 10 (02) : 45 - 48
  • [28] Low Power Approximate Multiplier Using Error Tolerant Adder
    Cho, Jaeik
    Kim, Youngmin
    2020 17TH INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC 2020), 2020, : 298 - 299
  • [29] A Road Truncation-Based Location Privacy-Preserving Method against Side-Weight Inference Attack
    Li, Qingyuan
    Wu, Hao
    Wu, Xiang
    Zhao, Ning
    Dong, Lan
    APPLIED SCIENCES-BASEL, 2022, 12 (03):
  • [30] New Approximate Multiplier for Low Power Digital Signal Processing
    Farshchi, Farzad
    Abrishami, Muhammad Saeed
    Fakhraie, Sied Mehdi
    2013 17TH CSI INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND DIGITAL SYSTEMS (CADS 2013), 2013, : 25 - 30