An overview of through-silicon-via technology and manufacturing challenges

被引：177

作者：

Gambino, Jeffrey P. ^{[1
]}

Adderly, Shawn A. ^{[1
]}

Knickerbocker, John U. ^{[2
]}

机构：

[1] IBM Microelect, Essex Jct, VT 05452 USA

[2] IBM Res, Yorktown Hts, NY 10598 USA

来源：

MICROELECTRONIC ENGINEERING | 2015年 / 135卷

关键词：

TSV; TSV manufacturing; TSV backside grind process; TSV reliability; TSV testing; 3D integration; HIGH-ASPECT-RATIO; ELECTROSTATIC DISCHARGE ESD; INTERCONNECT TECHNOLOGY; ATMOSPHERIC-PRESSURE; CU CONTAMINATION; TSV; INTEGRATION; STRESS; LAYER; SCALE;

D O I：

10.1016/j.mee.2014.10.019

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The idea of using through-silicon-via (TSV) technology has been around for many years. However, this technology has only recently been introduced into high volume manufacturing. This paper gives a comprehensive summary of the TSV fabrication steps, including etch, insulation, and metallization. Along with the backside processing, assembly, metrology, design, packaging, reliability, testing and yield challenges that arise with the use of TSVs. Benefits and drawbacks for using each approach to manufacture TSVs are discussed including via-first, via-middle, and the via-last process. Several applications for TSVs are discussed including memory arrays and image sensors. (C) 2015 Elsevier B.V. All rights reserved.

引用

页码：73 / 106

页数：34

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