A Power Supply Rejection Compensated External Capacitor-Less Low Drop-Out Regulator

This paper presents a compensation technique for a power supply rejection (PSR) improved external capacitor-less low drop-out (LDO) regulator. A replica circuit is used to cancel the power supply noise generated by the gate-source parasitic capacitor of the pass transistor. This design was fabricated in a 0.18 mu m bipolar-CMOS-DMOS (BCD) technology with a power supply of 1.8 V. The active core chip area is 0.023 mm(2), and the entire proposed LDO consumes 65 mu A of quiescent current. It has a drop-out voltage of 200 mV, and the maximum load current is 60 mA. The measured PSR has a maximum -22 dB enhancement compared with a conventional uncompensated LDO when delivering a current of 60 mA.