A Power Supply Rejection Compensated External Capacitor-Less Low Drop-Out Regulator

被引：0

作者：

Guo Tian ^{[1
]}

Moon, Jiho ^{[1
]}

Roh, Jeongjin ^{[1
]}

机构：

[1] Hanyang Univ, Dept Elect Engn, Ansan, South Korea

来源：

2019 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC) | 2019年

关键词：

external capacitor-less LDO; PSR compensated LDO; power management integrated circuit (PMIC);

D O I：

10.1109/isocc47750.2019.9027699

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a compensation technique for a power supply rejection (PSR) improved external capacitor-less low drop-out (LDO) regulator. A replica circuit is used to cancel the power supply noise generated by the gate-source parasitic capacitor of the pass transistor. This design was fabricated in a 0.18 mu m bipolar-CMOS-DMOS (BCD) technology with a power supply of 1.8 V. The active core chip area is 0.023 mm(2), and the entire proposed LDO consumes 65 mu A of quiescent current. It has a drop-out voltage of 200 mV, and the maximum load current is 60 mA. The measured PSR has a maximum -22 dB enhancement compared with a conventional uncompensated LDO when delivering a current of 60 mA.

引用

页码：54 / 55

页数：2

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