Settling Time Enhancement of Output Capacitor-Less Low-Dropout Regulator

被引：0
|
作者：
Kuo, Po-Yu [1 ]
Gao, Ting-Yao [1 ]
机构：
[1] Natl Yunlin Univ Sci & Technol, Dept Elect Engn, Touliu, Taiwan
来源：
2019 IEEE INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS - TAIWAN (ICCE-TW) | 2019年
关键词：
LDO REGULATOR;
D O I：
10.1109/icce-tw46550.2019.8991861
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
An output capacitor-less (OCL) low-dropout regulator (LDO) with a buffer and a slew-rate enhancement (SRE) circuit. By using the proposed SRE circuit, the transient response is improved. Moreover, the circuit stability can also be enhanced. The proposed voltage regulator is simulated by Spice simulation tool with a 5V power supply. From the simulation results, the proposed regulator provides a maximum load current of 100mA. The proposed regulator can achieve 33.12 ns settling time.
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页数：2
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