Automated Testing of Mixed-Signal Integrated Circuits by Topology Modification

被引：0

作者：

Coyette, Anthony ^{[1
]}

Esen, Baris ^{[1
]}

Vanhooren, Ronny ^{[1
]}

Dobbelaere, Wim ^{[1
]}

Gielen, Georges ^{[1
]}

机构：

[1] Katholieke Univ Leuven, Dept Elect Engn, Kasteelpk Arenberg 10, B-3001 Leuven, Belgium

来源：

2015 IEEE 33RD VLSI TEST SYMPOSIUM (VTS) | 2015年

关键词：

Design-for-Testability; controllability; observability; low-overhead; co-optimization; ANALOG;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A general method is proposed to automatically generate a DfT solution aiming at the detection of catastrophic faults in analog and mixed-signal integrated circuits. The approach consists in modifying the topology of the circuit by pulling up (down) nodes and then probing differentiating node voltages. The method generates a set of optimal hardware implementations addressing the multi-objective problem such that the fault coverage is maximized and the silicon overhead is minimized. The new method was applied to a real-case industrial circuit, demonstrating a nearly 100 percent coverage at the expense of an area increase of about 5 percent.

引用

页数：6

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