High density DRAM for space utilizing embedded DRAMs macros in 32nm SOI CMOS

被引：0

作者：

Popp, Jeremy ^{[1
]}

Ballast, John ^{[1
]}

Rabaa, Salim ^{[1
]}

McKay, Tony ^{[1
]}

Braatz, Jim ^{[1
]}

机构：

[1] Boeing Res & Technol, Bellevue, WA USA

来源：

2011 IEEE INTERNATIONAL SOI CONFERENCE | 2011年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页数：22

共 50 条

[31] A 20 Gbit/s RFDAC-based Direct-Modulation W-band Transmitter in 32nm SOI CMOS
Al-Rubaye, Hasan
Rebeiz, Gabriel M.
2016 IEEE COMPOUND SEMICONDUCTOR INTEGRATED CIRCUIT SYMPOSIUM (CSICS), 2016, : 206 - 209
[32] A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache
Barth, John
Plass, Don
Nelson, Erik
Hwang, Charlie
Fredeman, Gregory
Sperling, Michael
Mathews, Abraham
Kirihata, Toshiaki
Reohr, William R.
Nair, Kavita
Cao, Nianzheng
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2011, 46 (01) : 64 - 75
[33] A 69.5mW 20GS/s 6b Time-Interleaved ADC with Embedded Time-to-Digital Calibration in 32nm CMOS SOI
Chen, Vanessa Hung-Chu
Pileggi, Lawrence
2014 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS (ISSCC), 2014, 57 : 380 - +
[34] Three-Dimensional Wafer Stacking using Cu TSV integrated with 45nm high performance SOI-CMOS embedded DRAM technology
Batra, Pooja
LaTulipe, Douglas
Skordas, Spyridon
Winstel, Kevin
Kothandaraman, Chandrasekharan
Himmel, Ben
Maier, Gary
He, Bishan
Gamage, Deepal Wehella
Golz, John
Lin, Wei
Vo, Tuan
Priyadarshini, Deepika
Hubbard, Alex
Cauffman, Kristian
Peethala, Brown
Barth, John
Kirihata, Toshiaki
Graves-Abe, Troy
Robson, Norman
Iyer, Subramanian
2013 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S), 2013,
[35] A capacitor-less DRAM cell on 75nm gate length, 16nm thin fully depleted SOI device for high density embedded memories
Ranica, R
Villaret, A
Fenouillet-Beranger, C
Malinge, P
Mazoyer, P
Masson, P
Delille, D
Charbuillet, C
Candelier, P
Skotnicki, T
IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST, 2004, : 277 - 280
[36] A 32nm Low Power RF CMOS SOC Technology Featuring High-k/Metal Gate
VanDerVoorn, P.
Agostinelli, M.
Choi, S. -J.
Curello, G.
Deshpande, H.
El-Tanani, M. A.
Hafez, W.
Jalan, U.
Janbay, L.
Kang, M.
Koh, K. -J.
Komeyli, K.
Lakdawala, H.
Lin, J.
Lindert, N.
Mudanai, S.
Park, J.
Phoa, K.
Rahman, A.
Rizk, J.
Rockford, L.
Sacks, G.
Soumyanath, K.
Tashiro, H.
Taylor, S.
Tsai, C.
Xu, H.
Xu, J.
Yang, L.
Young, I.
Yeh, J. -Y.
Yip, J.
Bai, P.
Jan, C. -H.
2010 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2010, : 137 - +
[37] Reconfigurable X-Band 4x4 Butler Array in 32nm CMOS SOI for Angle-Reject Arrays
Tork, Amro
Natarajan, Arun
2016 IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM (IMS), 2016,
[38] A 0.039um2 High Performance eDRAM Cell based on 32nm High-K/Metal SOI Technology
Butt, N.
Mcstay, K.
Cestero, A.
Ho, H.
Kong, W.
Fang, S.
Krishnan, R.
Khan, B.
Tessier, A.
Davies, W.
Lee, S.
Zhang, Y.
Johnson, J.
Rombawa, S.
Takalkar, R.
Blauberg, A.
Hawkins, K. V.
Liu, J.
Rosenblatt, S.
Goyal, P.
Gupta, S.
Ervin, J.
Li, Z.
Galis, S.
Barth, J.
Yin, M.
Weaver, T.
Li, J. H.
Narasimha, S.
Parries, P.
Henson, W. K.
Robson, N.
Kirihata, T.
Chudzik, M.
Maciejewski, E.
Agnello, P.
Stiffler, S.
Iyer, S. S.
2010 INTERNATIONAL ELECTRON DEVICES MEETING - TECHNICAL DIGEST, 2010,
[39] A 0.001mm2 100μW On-chip Temperature Sensor with ±1.95°C (3σ) Inaccuracy In 32nm SOI CMOS
Chowdhury, Golam R.
Hassibi, Arjang
2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012), 2012, : 1999 - 2002
[40] 45nm CMOS platform technology (CMOS6) with high density embedded memories
Iwai, M
Oishi, A
Sanuki, T
Takegawa, Y
Komoda, T
Morimasa, Y
Ishimaru, K
Takayanagi, M
Eguchi, K
Matsushita, D
Muraoka, K
Sunouchi, K
Noguchi, T
2004 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2004, : 12 - 13

← 1 2 3 4 5 →