NUMANA: A Hybrid Numerical and Analytical Thermal Simulator for 3-D ICs

被引:0
|
作者
Lee, Yu-Min [1 ]
Wu, Tsung-Heng [1 ]
Huang, Pei-Yu [2 ]
Yang, Chi-Ping [1 ]
机构
[1] Natl Chiao Tung Univ, Hsinchu, Taiwan
[2] Ind Technol Res Inst, Hsinchu, Taiwan
关键词
D O I
暂无
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
By combining analytical and numerical simulation techniques, this work develops a hybrid thermal simulator, NUMANA, which can effectively deal with complicated material structures, to estimate the temperature profile of a 3-D IC. Compared with a commercial tool, ANSYS, its maximum relative error is only 1.84%. Compared with a well known linear system solver, SuperLU [1], it can achieve orders of magnitude speedup.
引用
收藏
页码:1379 / 1384
页数:6
相关论文
共 50 条
  • [31] Numerical Modeling of Physical Dispersion in Porous Rock - Implementation in 3-D Reservoir Simulator
    Golabek, Andrzej
    Szott, Wieslaw
    NAFTA-GAZ, 2016, 72 (07): : 528 - 533
  • [32] Enhanced Wafer Matching Heuristics for 3-D ICs
    Pavlidis, Vasilis F.
    Xu, Hu
    De Micheli, Giovanni
    2012 17TH IEEE EUROPEAN TEST SYMPOSIUM (ETS), 2012,
  • [33] 3-D ICs with TSVs:The hard work continues
    Jan Vardaman, E.
    Electronic Device Failure Analysis, 2013, 15 (03): : 46 - 47
  • [34] Thermal-WLP: A Transient Thermal Simulation Method Based on Weighted Laguerre Polynomials for 3-D ICs
    Liu, Sheng
    Wang, Cheng
    Yu, Zhengyong
    Tang, Wanchun
    Zhuang, Wei
    IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2017, 7 (03): : 405 - 411
  • [35] AC coupled interconnect for dense 3-D ICs
    Xu, J
    Mick, S
    Wilson, J
    Luo, L
    Chandrasekar, K
    Erickson, E
    Franzon, PD
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2004, 51 (05) : 2156 - 2160
  • [36] Advances in Design and Test of Monolithic 3-D ICs
    Chaudhuri, Arjun
    Banerjee, Sanmitra
    Park, Heechun
    Kim, Jinwoo
    Murali, Gauthaman
    Lee, Edward
    Kim, Daehyun
    Lim, Sung Kyu
    Mukhopadhyay, Saibal
    Chakrabarty, Krishnendu
    IEEE DESIGN & TEST, 2020, 37 (04) : 92 - 100
  • [37] SOC Test Architecture and Method for 3-D ICs
    Lo, Chih-Yen
    Hsing, Yu-Tsao
    Denq, Li-Ming
    Wu, Cheng-Wen
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2010, 29 (10) : 1645 - 1649
  • [38] Scaling trends of power noise in 3-D ICs
    Xu, Kan
    Friedman, Eby G.
    INTEGRATION-THE VLSI JOURNAL, 2015, 51 : 139 - 148
  • [39] Temperature Sensing RRAM Architecture for 3-D ICs
    Merkel, Cory E.
    Kudithipudi, Dhireesha
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2014, 22 (04) : 878 - 887
  • [40] Hierarchical Test Integration Methodology for 3-D ICs
    Chou, Che-Wei
    Li, Jin-Fu
    Yu, Yun-Chao
    Lo, Chih-Yen
    Kwai, Ding-Ming
    Chou, Yung-Fa
    IEEE DESIGN & TEST, 2015, 32 (04) : 59 - 70