Hierarchical Test Integration Methodology for 3-D ICs

被引：3
|
作者：
Chou, Che-Wei [1 ]
Li, Jin-Fu [1 ]
Yu, Yun-Chao [2 ]
Lo, Chih-Yen [3 ]
Kwai, Ding-Ming [4 ]
Chou, Yung-Fa [4 ]
机构：
[1] Natl Cent Univ, Dept Elect Engn, Taoyuan 320, Taiwan
[2] Natl Cent Univ, Taoyuan 320, Taiwan
[3] Ind Technol Res Inst, Informat & Commun Res Labs ICL, Integrated Circuit Dept 3D, Hsinchu, Taiwan
[4] Ind Technol Res Inst, Informat & Commun Res Labs ICL, Hsinchu, Taiwan
来源：
IEEE DESIGN & TEST | 2015年 / 32卷 / 04期
关键词：
D O I：
10.1109/MDAT.2015.2427257
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
引用
收藏
页码：59 / 70
页数：12
相关论文
共 50 条
  • [1] Advances in Design and Test of Monolithic 3-D ICs
    Chaudhuri, Arjun
    Banerjee, Sanmitra
    Park, Heechun
    Kim, Jinwoo
    Murali, Gauthaman
    Lee, Edward
    Kim, Daehyun
    Lim, Sung Kyu
    Mukhopadhyay, Saibal
    Chakrabarty, Krishnendu
    [J]. IEEE DESIGN & TEST, 2020, 37 (04) : 92 - 100
  • [2] SOC Test Architecture and Method for 3-D ICs
    Lo, Chih-Yen
    Hsing, Yu-Tsao
    Denq, Li-Ming
    Wu, Cheng-Wen
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2010, 29 (10) : 1645 - 1649
  • [3] A Robust Integrated Power Delivery Methodology for 3-D ICs
    Safari, Yousef
    Vaisband, Boris
    [J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2023, 31 (03) : 287 - 295
  • [4] Hier-3D: A Methodology for Physical Hierarchy Exploration of 3-D ICs
    Bethur, Nesara Eranna
    Agnesina, Anthony
    Brunion, Moritz
    Garcia-Ortiz, Alberto
    Catthoor, Francky
    Milojevic, Dragomir
    Komalan, Manu
    Cavalcante, Matheus
    Riedel, Samuel
    Benini, Luca
    Lim, Sung Kyu
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2024, 43 (07) : 1957 - 1970
  • [5] Wafer Level Integration of 3-D Heat Sinks in Power ICs
    Para, Isabella
    Marasso, S. L.
    Perrone, D.
    Gentile, M. G.
    Sanfilippo, C.
    Richieri, Giovanni
    Merlin, Luigi
    Pugliese, D.
    Cocuzza, M.
    Ferrero, S.
    Scaltrito, L.
    Pirri, C. F.
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2017, 64 (10) : 4226 - 4232
  • [6] Probe-Pad Placement for Prebond Test of 3-D ICs
    Panth, Shreepad
    Lim, Sung Kyu
    [J]. IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2016, 6 (04): : 637 - 644
  • [7] A Test Response Compression Method for Monolithic 3-D ICs Based on 3-D Haar Wavelet Transforms
    Hu, Jing
    Lin, Yuheng
    Hu, Ming
    Wang, Hongjian
    [J]. IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, 2021, 70
  • [8] Thermal Pathfinding for 3-D ICs
    Priyadarshi, Shivam
    Davis, W. Rhett
    Steer, Michael B.
    Franzon, Paul D.
    [J]. IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2014, 4 (07): : 1159 - 1168
  • [9] A Post-Bond ILV Test Method in Monolithic 3-D ICs
    Fang, Xu
    Zhao, Xiaofeng
    [J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2024,
  • [10] Scan Test of Die Logic in 3-D ICs Using TSV Probing
    Noia, Brandon
    Panth, Shreepad
    Chakrabarty, Krishnendu
    Lim, Sung Kyu
    [J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2015, 23 (02) : 317 - 330
12345