Super junction LDMOS with P-trench and stepped buried oxide layer for high performance

被引:3
|
作者
Tang, Pan-pan [1 ]
Wang, Ying [2 ]
Cao, Fei [2 ]
Yu, Cheng-hao [2 ]
Bao, Meng-tian [1 ]
Luo, Xin [1 ]
机构
[1] Harbin Engn Univ, Coll Informat & Commun Engn, Harbin 150001, Heilongjiang, Peoples R China
[2] Hangzhou Dianzi Univ, Key Lab RF Circuits & Syst, Minist Educ, Hangzhou 310018, Zhejiang, Peoples R China
基金
美国国家科学基金会;
关键词
Breakdown voltage; LDMOS; Specific on-resistance; Silicon-on-insulator (SOI); HIGH-VOLTAGE DEVICE; ELECTRIC-FIELD; BREAKDOWN VOLTAGE; SUPERJUNCTION LDMOS; ON-RESISTANCE; POWER MOSFETS; SOI; TRANSISTORS; SIMULATION; IMPROVE;
D O I
10.1016/j.spmi.2018.11.005
中图分类号
O469 [凝聚态物理学];
学科分类号
070205 ;
摘要
In this paper, a new silicon-on-insulator superjunction lateral double-diffused MOSFET (SOI SJLDMOS) with a p-trench layer and stepped buried oxide, is investigated using 3D numerical simulation. The p-trench layer and stepped buried oxide distinguish it from a conventional SOI SJLDMOS. The etched buried oxide layer, with its stepped buried -oxide structure, which facilitates a more even electric field distribution via the electric field modulation effect, increases the breakdown-voltage (BV). Furthermore, the p-trench layer improves the doping concentration through compensation depletion, which further decreases the specific on-resistance (R-on,R-sp). The simulation indicates that the new device has a higher BV (increased by 29%) than the conventional SOI SJLDMOS. At the same time, R-on,R-sp decreases by 20% for the on-state for a given drift-region length.
引用
收藏
页码:198 / 204
页数:7
相关论文
共 50 条
  • [1] A novel LDMOS structure using P-trench for high performance applications
    Orouji, Ali A.
    Mansoori, Hojjat Allah
    Dideban, A.
    Shahnazarisani, Hadi
    MATERIALS SCIENCE IN SEMICONDUCTOR PROCESSING, 2015, 39 : 654 - 658
  • [2] Super junction LDMOS with step field oxide layer
    Cao, Zhen
    Duan, Baoxing
    Yuan, Xiaoning
    Yuan, Song
    Yang, Yintang
    MICRO & NANO LETTERS, 2016, 11 (11): : 666 - 669
  • [3] A deep trench super-junction LDMOS with double charge compensation layer
    Lijuan Wu
    Shaolian Su
    Xing Chen
    Jinsheng Zeng
    Haifeng Wu
    Journal of Semiconductors, 2022, 43 (10) : 107 - 112
  • [4] A deep trench super-junction LDMOS with double charge compensation layer
    Lijuan Wu
    Shaolian Su
    Xing Chen
    Jinsheng Zeng
    Haifeng Wu
    Journal of Semiconductors, 2022, (10) : 107 - 112
  • [5] A deep trench super-junction LDMOS with double charge compensation layer
    Wu, Lijuan
    Su, Shaolian
    Chen, Xing
    Zeng, Jinsheng
    Wu, Haifeng
    JOURNAL OF SEMICONDUCTORS, 2022, 43 (10)
  • [6] Improved SOI LDMOS performance by using a partial stepped polysilicon layer as the buried layer
    Guo, Jingwei
    Hu, Shengdong
    Huang, Ye
    Yuan, Qi
    Yang, Dong
    Yang, Ling
    You, Liang
    Yu, Jianyi
    MATERIALS SCIENCE IN SEMICONDUCTOR PROCESSING, 2019, 90 : 7 - 12
  • [7] The Simulation Study of the SOI Trench LDMOS With Lateral Super Junction
    Chen, Weizhong
    He, Lijun
    Han, Zhengsheng
    Huang, Yi
    IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, 2018, 6 (01): : 708 - 713
  • [8] A Novel High Performance SOI LDMOS with Buried Stepped Gate Field Plate
    Hu, Hongchao
    Dai, Hongli
    Wang, Luoxin
    Lyu, Haitao
    Xue, Yuming
    Qian, Tu
    TRANSACTIONS ON ELECTRICAL AND ELECTRONIC MATERIALS, 2023, 24 (06) : 538 - 546
  • [9] A Novel High Performance SOI LDMOS with Buried Stepped Gate Field Plate
    Hongchao Hu
    Hongli Dai
    Luoxin Wang
    Haitao Lyu
    Yuming Xue
    Tu Qian
    Transactions on Electrical and Electronic Materials, 2023, 24 : 538 - 546
  • [10] Simulation Study of a Super-Junction Deep-Trench LDMOS With a Trapezoidal Trench
    Cheng, Junji
    Li, Ping
    Chen, Weizhen
    Yi, Bo
    Chen, Xing Bi
    IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, 2018, 6 (01): : 1091 - 1096