A gated clock scheme for low power scan-based BIST

被引：4
|
作者：
Bonhomme, Y [1 ]
Girard, P [1 ]
Guiller, L [1 ]
Landrault, C [1 ]
Pravossoudovitch, S [1 ]
机构：
[1] Univ Montpellier 2, Lab Informat Robot & Microelect Montpellier, CNRS, F-34392 Montpellier 5, France
来源：
SEVENTH IEEE INTERNATIONAL ON-LINE TESTING WORKSHOP, PROCEEDINGS | 2001年
关键词：
D O I：
10.1109/OLT.2001.937824
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper, we present a new low power scan-based BIST technique which can reduce the switching activity during test operation. The proposed low power /energy technique is based on a gated clock scheme for the scan path and the clock tree feeding the scan path.
引用
收藏
页码：87 / 89
页数：3
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