A Compact Model for ISPP of 3-D Charge-Trap NAND Flash Memories

被引：15
|
作者：
Kim, Minsoo [1 ]
Kim, Sungbak [2 ]
Shin, Hyungcheol [1 ]
机构：
[1] Seoul Natl Univ, Interuniv Semicond Res Ctr, Sch Elect Engn & Comp Sci, Seoul 151742, South Korea
[2] SK Hynix Inc, Flash Adv Design Team, Icheon Si 17336, South Korea
来源：
IEEE TRANSACTIONS ON ELECTRON DEVICES | 2020年 / 67卷 / 08期
关键词：
3-D charge-trap NAND flash memories; compact model; incremental step pulse programming (ISPP); program transient operation; simulation program with integrated circuit emphasis (SPICE); RETENTION CHARACTERISTICS;
D O I：
10.1109/TED.2020.3000448
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
We developed a compact model for program transient simulation of 3-D charge-trap NAND flash on a bitline (BL) string level. By implanting the trapped charge parameters and the solutions obtained from modified 1-D Poisson equation into our unit cell model, we suggest that our model shows better accuracy compared to the existing model. After fitting the measured incremental step pulse programming (ISPP) data with the best accuracy, we investigated our model dependence on parameters relevant to electron tunneling/capture/emission and channel scaling. Also, the simulation results from various pulse conditions are investigated. Finally, program-inhibit characteristics by isolated channel were simulated and analyzed. Thus, we propose a widely available, highly accurate, and physics-based compact model for program operation of 3-D charge-trap NAND flash memories.
引用
收藏
页码：3095 / 3101
页数：7
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