共 50 条
- [1] Enhancement of signal integrity and power integrity with embedded capacitors in high-speed packages [J]. ISQED 2006: PROCEEDINGS OF THE 7TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, 2006, : 284 - +
- [3] Advanced Parallel Algorithm for System-Level EMC Modeling of High-Speed Electronic Package [J]. 2008 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY, VOLS 1-3, 2008, : 763 - 767
- [4] A System-Level Equivalent Circuit Method for the Electrical Performance Modeling of Electronic Packages [J]. 2010 11TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY & HIGH DENSITY PACKAGING (ICEPT-HDP), 2010, : 683 - 686
- [5] Signal integrity optimization of high-speed VLSI packages and interconnects [J]. 48TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE - 1998 PROCEEDINGS, 1998, : 1073 - 1076
- [6] Signal integrity and EMC in high-speed electronic package integration [J]. 2007 ASIA-PACIFIC CONFERENCE ON APPLIED ELECTROMAGNETICS, PROCEEDINGS, 2007, : 7 - 10
- [8] Layout Parameter Optimization Based Power and Signal Integrity Performance Improvement of High-Speed Interfaces of Wirebond Packages [J]. 2013 IEEE 63RD ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2013, : 2107 - 2112
- [9] Sparsity Constrained Regression For High-Speed Signal Integrity Modeling [J]. 2019 ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS (EDAPS 2019), 2019,
- [10] Signal Integrity: Fault Modeling and Testing in High-Speed SoCs [J]. Journal of Electronic Testing, 2002, 18 : 539 - 554