共 50 条
- [41] A semi-analytical approach for system-level electrical modeling of electronic packages with large number of vias [J]. IEEE TRANSACTIONS ON ADVANCED PACKAGING, 2008, 31 (02): : 267 - 274
- [42] Effects of High-Speed Signals on Power Integrity [J]. PROCEEDINGS OF 2018 29TH INTERNATIONAL CONFERENCE ON ELECTRICAL CONTACTS AND 64TH IEEE HOLM CONFERENCE ON ELECTRICAL CONTACTS, 2018, : 278 - 285
- [43] Modeling Power Consumption at System-Level for Design of Power Integrity-Aware AMS-Circuits [J]. 2015 18TH FORUM ON SPECIFICATION AND DESIGN LANGUAGES (FDL), 2015, : 32 - 39
- [44] MODELING OF HIGH-SPEED ELECTRONIC DEVICES [J]. VISNYK NTUU KPI SERIIA-RADIOTEKHNIKA RADIOAPARATOBUDUVANNIA, 2013, (54): : 151 - 159
- [45] Signal Integrity Analysis and Simulation of High-speed Circuit [J]. PROCEEDINGS 2016 EIGHTH INTERNATIONAL CONFERENCE ON MEASURING TECHNOLOGY AND MECHATRONICS AUTOMATION ICMTMA 2016, 2016, : 593 - 596
- [47] Signal Integrity Characterization of High-Speed DDR Interface [J]. 2011 IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS SYMPOSIUM (EDAPS), 2011,
- [48] CLOCK AND SIGNAL INTEGRITY FOR TESTING HIGH-SPEED ADCS [J]. ELECTRONICS WORLD, 2011, 117 (1908): : 14 - 17
- [49] High-Speed Signal Integrity Design for HDCA Systems [J]. 2018 INTERNATIONAL CONFERENCE ON INFORMATION AND COMMUNICATION TECHNOLOGY CONVERGENCE (ICTC), 2018, : 1267 - 1269