Method for System-Level Signal and Power Integrity Modeling of High-Speed Electronic Packages

被引:0
|
作者
Liu, En-Xiao [1 ]
Wei, Xingchang [1 ]
Oo, Zaw Zaw [1 ]
Zhang, Yao-Jiang [1 ]
Zhang, Wenzu [1 ]
Li, Er-Ping [1 ]
机构
[1] A STAR Inst High Performance Comp, Adv Electromagnet & Elect Lab, Singapore 138632, Singapore
关键词
EFFICIENT; SIMULATION; EQUATION; PLANE; VIAS;
D O I
10.1109/EPTC.2009.5416566
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper reported the latest development of the modal decomposition with T-matrix method for accurate and efficient analysis of coupling of multiple vias in finite-sized multilayered parallel-plate structures. A novel boundary modeling method, named the frequency-dependent cylinder layer (FDCL), is proposed to resolve the open problem of boundary modeling associated with modal expansion methods. Moreover, a generalized T matrix model derived by the mode matching technique, is created to characterize the coupling effect for vias penetrating more than one layer in a multilayered structure. Both numerical and experimental verifications are presented to validate the new modeling methods. The above method has been incorporated into the simulation tool developed recently by us.
引用
收藏
页码:96 / 101
页数:6
相关论文
共 50 条
  • [41] A semi-analytical approach for system-level electrical modeling of electronic packages with large number of vias
    Oo, Zaw Zaw
    Liu, En-Xiao
    Li, Er-Ping
    Wei, Xingchang
    Zhang, Yaojiang
    Tan, Mark
    Li, Le-Wei Joshua
    Vahldieck, Ruediger
    [J]. IEEE TRANSACTIONS ON ADVANCED PACKAGING, 2008, 31 (02): : 267 - 274
  • [42] Effects of High-Speed Signals on Power Integrity
    Smith, Stephen B.
    Pater, Khushhoo
    Cin, Joseph
    Agili, Sedig S.
    Waldens, Jeffrey
    [J]. PROCEEDINGS OF 2018 29TH INTERNATIONAL CONFERENCE ON ELECTRICAL CONTACTS AND 64TH IEEE HOLM CONFERENCE ON ELECTRICAL CONTACTS, 2018, : 278 - 285
  • [43] Modeling Power Consumption at System-Level for Design of Power Integrity-Aware AMS-Circuits
    Pan, Xiao
    Molina, Javier Moreno
    Grimm, Christoph
    [J]. 2015 18TH FORUM ON SPECIFICATION AND DESIGN LANGUAGES (FDL), 2015, : 32 - 39
  • [44] MODELING OF HIGH-SPEED ELECTRONIC DEVICES
    Kudrya, V. G.
    [J]. VISNYK NTUU KPI SERIIA-RADIOTEKHNIKA RADIOAPARATOBUDUVANNIA, 2013, (54): : 151 - 159
  • [45] Signal Integrity Analysis and Simulation of High-speed Circuit
    Zhu Xiaoyan
    Wang Zhao
    [J]. PROCEEDINGS 2016 EIGHTH INTERNATIONAL CONFERENCE ON MEASURING TECHNOLOGY AND MECHATRONICS AUTOMATION ICMTMA 2016, 2016, : 593 - 596
  • [47] Signal Integrity Characterization of High-Speed DDR Interface
    Kato, Takuya
    Yamamoto, Shintaro
    Sudo, Toshio
    Ono, Yasushi
    Takahashi, Eiji
    Yamada, Toru
    [J]. 2011 IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS SYMPOSIUM (EDAPS), 2011,
  • [48] CLOCK AND SIGNAL INTEGRITY FOR TESTING HIGH-SPEED ADCS
    Okawara, Hideo
    [J]. ELECTRONICS WORLD, 2011, 117 (1908): : 14 - 17
  • [49] High-Speed Signal Integrity Design for HDCA Systems
    Kwon, Wonok
    Kim, Young Woo
    [J]. 2018 INTERNATIONAL CONFERENCE ON INFORMATION AND COMMUNICATION TECHNOLOGY CONVERGENCE (ICTC), 2018, : 1267 - 1269
  • [50] Surrogate Modeling of High-Speed Links Based on GNN and RNN for Signal Integrity Applications
    Li, Zheng
    Li, Xiao-Chun
    Wu, Ze-Ming
    Zhu, Yu
    Mao, Jun-Fa
    [J]. IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, 2023, 71 (09) : 3784 - 3796