Modeling Power Consumption at System-Level for Design of Power Integrity-Aware AMS-Circuits

Among many challenges in designing reliable integrated circuits and embedded systems, the power integrity (PI-) issue is a particularly critical one. Researches and CAD tools have been carried out in the last decades. However, all of them address the problem from a circuit-level perspective. Moreover, the PI-problem cannot be completely verified until layout, the final stage of the design phase. In this paper we propose a new approach to model power consumption that allows PI-simulation at the system level of abstraction, by extending the state-machine based power estimation method. For this purpose, we model power consumption in power states which also includes a statistical model, and in state-transitions modeled by transfer function. The proposed approach is implemented as part of a simulation framework, which uses SystemC-AMS, and is applied on a battery management IC design.