12.2 GHz All-digital PLL with Pattern Memorizing Cells for Low Power/low Jitter using 65 nm CMOS Process

被引：0

作者：

Lee, Sanggeun ^{[1
]}

Oh, Taehyoun ^{[1
]}

机构：

[1] Kwangwoon Univ, Dept Elect Engn, 615 Bima Build,20 Gwangun Ro, Seoul 139701, South Korea

来源：

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE | 2021年 / 21卷 / 02期

基金：

新加坡国家研究基金会;

关键词：

PLL; digital PLL; frequency control word; pattern memory;

D O I：

10.5573/JSTS.2021.21.2.152

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A system level power/jitter reduction technique of all-digital phase locked loop (ADPLL) design has been developed. The architecture to memorize the repetitive control signal pattern of digitally-controlled oscillator (DCO) during lock state and to regenerate the pattern, achieve the reduced power consumption compared to conventional mode from 14.4 mW to 9.51 mW in 1.0 V supply at 12.2 GHz and concurrently reduce jitter from 1.86 ps to 1.56 ps. The prototype PLL has been fabricated in 65 nm CMOS process and occupies 0.16 mm(2) chip area.

引用

页码：152 / 156

页数：5

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